/linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn20/ |
H A D | hw_translate_dcn20.c | 54 #undef REG macro 55 #define REG(reg_name)\ macro 73 case REG(DC_GPIO_GENERIC_A): 103 case REG(DC_GPIO_HPD_A): 129 /* REG(DC_GPIO_GENLK_MASK */ 130 case REG(DC_GPIO_GENLK_A): 155 case REG(DC_GPIO_DDC1_A): 158 case REG(DC_GPIO_DDC2_A): 161 case REG(DC_GPIO_DDC3_A): 164 case REG(DC_GPIO_DDC4_ [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dpp/dcn30/ |
H A D | dcn30_dpp_cm.c | 33 #define REG(reg)\ macro 244 gam_regs.start_cntl_b = REG(CM_GAMCOR_RAMB_START_CNTL_B); 245 gam_regs.start_cntl_g = REG(CM_GAMCOR_RAMB_START_CNTL_G); 246 gam_regs.start_cntl_r = REG(CM_GAMCOR_RAMB_START_CNTL_R); 247 gam_regs.start_slope_cntl_b = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_B); 248 gam_regs.start_slope_cntl_g = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_G); 249 gam_regs.start_slope_cntl_r = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_R); 250 gam_regs.start_end_cntl1_b = REG(CM_GAMCOR_RAMB_END_CNTL1_B); 251 gam_regs.start_end_cntl2_b = REG(CM_GAMCOR_RAMB_END_CNTL2_B); 252 gam_regs.start_end_cntl1_g = REG(CM_GAMCOR_RAMB_END_CNTL1_ [all...] |
/linux-master/drivers/accel/ivpu/ |
H A D | ivpu_hw_reg_io.h | 33 #define REG_FLD(REG, FLD) \ 34 (REG##_##FLD##_MASK) 35 #define REG_FLD_NUM(REG, FLD, num) \ 36 FIELD_PREP(REG##_##FLD##_MASK, num) 37 #define REG_GET_FLD(REG, FLD, val) \ 38 FIELD_GET(REG##_##FLD##_MASK, val) 39 #define REG_CLR_FLD(REG, FLD, val) \ 40 ((val) & ~(REG##_##FLD##_MASK)) 41 #define REG_SET_FLD(REG, FLD, val) \ 42 ((val) | (REG## [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dcn30/ |
H A D | dcn30_dwb_cm.c | 36 #define REG(reg)\ macro 89 gam_regs.start_cntl_b = REG(DWB_OGAM_RAMA_START_CNTL_B); 90 gam_regs.start_cntl_g = REG(DWB_OGAM_RAMA_START_CNTL_G); 91 gam_regs.start_cntl_r = REG(DWB_OGAM_RAMA_START_CNTL_R); 92 gam_regs.start_base_cntl_b = REG(DWB_OGAM_RAMA_START_BASE_CNTL_B); 93 gam_regs.start_base_cntl_g = REG(DWB_OGAM_RAMA_START_BASE_CNTL_G); 94 gam_regs.start_base_cntl_r = REG(DWB_OGAM_RAMA_START_BASE_CNTL_R); 95 gam_regs.start_slope_cntl_b = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_B); 96 gam_regs.start_slope_cntl_g = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_G); 97 gam_regs.start_slope_cntl_r = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_ [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn315/ |
H A D | hw_translate_dcn315.c | 54 #undef REG macro 55 #define REG(reg_name)\ macro 73 case REG(DC_GPIO_GENERIC_A): 103 case REG(DC_GPIO_HPD_A): 129 /* REG(DC_GPIO_GENLK_MASK */ 130 case REG(DC_GPIO_GENLK_A): 155 case REG(DC_GPIO_DDC1_A): 158 case REG(DC_GPIO_DDC2_A): 161 case REG(DC_GPIO_DDC3_A): 164 case REG(DC_GPIO_DDC4_ [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn32/ |
H A D | hw_translate_dcn32.c | 52 #undef REG macro 53 #define REG(reg_name)\ macro 71 case REG(DC_GPIO_GENERIC_A): 98 case REG(DC_GPIO_HPD_A): 121 /* REG(DC_GPIO_GENLK_MASK */ 122 case REG(DC_GPIO_GENLK_A): 146 case REG(DC_GPIO_DDC1_A): 149 case REG(DC_GPIO_DDC2_A): 152 case REG(DC_GPIO_DDC3_A): 155 case REG(DC_GPIO_DDC4_ [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn21/ |
H A D | hw_translate_dcn21.c | 54 #undef REG macro 55 #define REG(reg_name)\ macro 72 case REG(DC_GPIO_GENERIC_A): 102 case REG(DC_GPIO_HPD_A): 128 /* REG(DC_GPIO_GENLK_MASK */ 129 case REG(DC_GPIO_GENLK_A): 154 case REG(DC_GPIO_DDC1_A): 157 case REG(DC_GPIO_DDC2_A): 160 case REG(DC_GPIO_DDC3_A): 163 case REG(DC_GPIO_DDC4_ [all...] |
/linux-master/arch/loongarch/include/uapi/asm/ |
H A D | kvm.h | 81 #define LOONGARCH_REG_64(TYPE, REG) (TYPE | KVM_REG_SIZE_U64 | (REG << LOONGARCH_REG_SHIFT)) 82 #define KVM_IOC_CSRID(REG) LOONGARCH_REG_64(KVM_REG_LOONGARCH_CSR, REG) 83 #define KVM_IOC_CPUCFG(REG) LOONGARCH_REG_64(KVM_REG_LOONGARCH_CPUCFG, REG)
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/linux-master/drivers/gpu/drm/i915/gt/ |
H A D | intel_lrc.c | 36 * number of registers. They are set by using the REG/REG16 macros: the former 54 #define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200)) macro 110 REG(0x034), 111 REG(0x030), 112 REG(0x038), 113 REG(0x03c), 114 REG(0x168), 115 REG(0x140), 116 REG(0x110), 117 REG( 637 #undef REG macro [all...] |
/linux-master/drivers/spi/ |
H A D | spi-realtek-rtl.c | 30 #define REG(x) (rtspi->base + x) macro 39 value = readl(REG(RTL_SPI_SFCSR)); 44 writel(value, REG(RTL_SPI_SFCSR)); 51 value = readl(REG(RTL_SPI_SFCSR)); 57 writel(value, REG(RTL_SPI_SFCSR)); 62 while (!(readl(REG(RTL_SPI_SFCSR)) & RTL_SPI_SFCSR_RDY)) 69 writel(*buf, REG(RTL_SPI_SFDR)); 76 writel(buf[0] << 24, REG(RTL_SPI_SFDR)); 83 *buf = readl(REG(RTL_SPI_SFDR)); 90 *buf = readl(REG(RTL_SPI_SFD [all...] |
/linux-master/drivers/gpu/drm/xe/ |
H A D | xe_lrc.c | 96 * number of registers. They are set by using the REG/REG16 macros: the former 114 #define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200)) macro 163 REG(0x034), 164 REG(0x030), 165 REG(0x038), 166 REG(0x03c), 167 REG(0x168), 168 REG(0x140), 169 REG(0x110), 170 REG( 512 #undef REG macro [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dpp/dcn10/ |
H A D | dcn10_dpp_cm.c | 42 #define REG(reg)\ macro 125 gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12); 126 gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34); 135 gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12); 136 gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34); 145 gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12); 146 gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34); 203 gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12); 204 gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34); 213 gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C1 [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn301/ |
H A D | dcn301_hwseq.c | 35 #define REG(reg)\ macro
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/linux-master/drivers/irqchip/ |
H A D | irq-realtek-rtl.c | 26 #define REG(x) (realtek_ictl_base + x) macro 58 value = readl(REG(RTL_ICTL_GIMR)); 60 writel(value, REG(RTL_ICTL_GIMR)); 72 value = readl(REG(RTL_ICTL_GIMR)); 74 writel(value, REG(RTL_ICTL_GIMR)); 92 write_irr(REG(RTL_ICTL_IRR0), hw, 1); 111 pending = readl(REG(RTL_ICTL_GIMR)) & readl(REG(RTL_ICTL_GISR)); 138 writel(0, REG(RTL_ICTL_GIMR)); 140 write_irr(REG(RTL_ICTL_IRR [all...] |
/linux-master/drivers/net/ipa/reg/ |
H A D | gsi_reg-v3.1.c | 13 REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk, 16 REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk, 176 REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP); 178 REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x0001f088 + 0x4000 * GSI_EE_AP); 180 REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP); 182 REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0001f094 + 0x4000 * GSI_EE_AP); 184 REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk, 187 REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk, 190 REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr, 193 REG(CNTXT_SRC_EV_CH_IRQ_CL [all...] |
H A D | gsi_reg-v3.5.1.c | 13 REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk, 16 REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk, 187 REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP); 189 REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x0001f088 + 0x4000 * GSI_EE_AP); 191 REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP); 193 REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0001f094 + 0x4000 * GSI_EE_AP); 195 REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk, 198 REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk, 201 REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr, 204 REG(CNTXT_SRC_EV_CH_IRQ_CL [all...] |
H A D | gsi_reg-v4.0.c | 13 REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk, 16 REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk, 192 REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP); 194 REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x0001f088 + 0x4000 * GSI_EE_AP); 196 REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP); 198 REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0001f094 + 0x4000 * GSI_EE_AP); 200 REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk, 203 REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk, 206 REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr, 209 REG(CNTXT_SRC_EV_CH_IRQ_CL [all...] |
H A D | gsi_reg-v4.9.c | 13 REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk, 16 REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk, 196 REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x00012080 + 0x4000 * GSI_EE_AP); 198 REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x00012088 + 0x4000 * GSI_EE_AP); 200 REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x00012090 + 0x4000 * GSI_EE_AP); 202 REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x00012094 + 0x4000 * GSI_EE_AP); 204 REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk, 207 REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk, 210 REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr, 213 REG(CNTXT_SRC_EV_CH_IRQ_CL [all...] |
H A D | gsi_reg-v4.5.c | 13 REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk, 16 REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk, 195 REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x00012080 + 0x4000 * GSI_EE_AP); 197 REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x00012088 + 0x4000 * GSI_EE_AP); 199 REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x00012090 + 0x4000 * GSI_EE_AP); 201 REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x00012094 + 0x4000 * GSI_EE_AP); 203 REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk, 206 REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk, 209 REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr, 212 REG(CNTXT_SRC_EV_CH_IRQ_CL [all...] |
H A D | gsi_reg-v4.11.c | 13 REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk, 16 REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk, 197 REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x00012080 + 0x4000 * GSI_EE_AP); 199 REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x00012088 + 0x4000 * GSI_EE_AP); 201 REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x00012090 + 0x4000 * GSI_EE_AP); 203 REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x00012094 + 0x4000 * GSI_EE_AP); 205 REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk, 208 REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk, 211 REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr, 214 REG(CNTXT_SRC_EV_CH_IRQ_CL [all...] |
H A D | gsi_reg-v5.0.c | 13 REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk, 16 REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk, 189 REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x00025080 + 0x12000 * GSI_EE_AP); 191 REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x00025088 + 0x12000 * GSI_EE_AP); 193 REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x00025090 + 0x12000 * GSI_EE_AP); 195 REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk, 198 REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr, 201 REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0002509c + 0x12000 * GSI_EE_AP); 203 REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk, 206 REG(CNTXT_SRC_EV_CH_IRQ_CL [all...] |
/linux-master/arch/arm64/kernel/ |
H A D | hw_breakpoint.c | 60 #define READ_WB_REG_CASE(OFF, N, REG, VAL) \ 62 AARCH64_DBG_READ(N, REG, VAL); \ 65 #define WRITE_WB_REG_CASE(OFF, N, REG, VAL) \ 67 AARCH64_DBG_WRITE(N, REG, VAL); \ 70 #define GEN_READ_WB_REG_CASES(OFF, REG, VAL) \ 71 READ_WB_REG_CASE(OFF, 0, REG, VAL); \ 72 READ_WB_REG_CASE(OFF, 1, REG, VAL); \ 73 READ_WB_REG_CASE(OFF, 2, REG, VAL); \ 74 READ_WB_REG_CASE(OFF, 3, REG, VAL); \ 75 READ_WB_REG_CASE(OFF, 4, REG, VA [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/ |
H A D | dcn20_mpc.c | 33 #define REG(reg)\ macro 170 ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]); 171 ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]); 173 ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_B[opp_id]); 174 ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_B[opp_id]); 229 ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]); 230 ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]); 232 ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_B[opp_id]); 233 ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_B[opp_id]); 330 gam_regs.start_cntl_b = REG(MPCC_OGAM_RAMB_START_CNTL_ [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/gpio/ |
H A D | ddc_regs.h | 35 .type ## _reg = REG(DC_GPIO_DDC ## id ## _ ## type),\ 49 .ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP) 53 .ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP),\ 54 .phy_aux_cntl = REG(PHY_AUX_CNTL), \ 55 .dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5) 58 .type ## _reg = REG(DC_GPIO_DDCVGA_ ## type),\ 75 .type ## _reg = REG(DC_GPIO_I2CPAD_ ## type),\ 94 .phy_aux_cntl = REG(PHY_AUX_CNTL), \ 95 .dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5)
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/linux-master/arch/loongarch/include/asm/ |
H A D | hw_breakpoint.h | 57 #define LOONGARCH_CSR_WATCH_READ(N, REG, T, VAL) \ 60 VAL = csr_read64(LOONGARCH_CSR_##IB##N##REG); \ 62 VAL = csr_read64(LOONGARCH_CSR_##DB##N##REG); \ 65 #define LOONGARCH_CSR_WATCH_WRITE(N, REG, T, VAL) \ 68 csr_write64(VAL, LOONGARCH_CSR_##IB##N##REG); \ 70 csr_write64(VAL, LOONGARCH_CSR_##DB##N##REG); \
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