/linux-master/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/ |
H A D | pixelgen_public.h | 28 * @param[in] id The global unique ID of the pixelgen controller. 32 const pixelgen_ID_t ID, 38 * @param[in] id The global unique ID of the pixelgen controller. 42 const pixelgen_ID_t ID, 55 * @param[in] ID The global unique ID for the pixelgen instance. 61 const pixelgen_ID_t ID, 67 * @param[in] ID The global unique ID for the pixelgen. 73 const pixelgen_ID_t ID, [all...] |
H A D | fifo_monitor_public.h | 27 \param ID[in] FIFO_MONITOR identifier 34 const fifo_monitor_ID_t ID, 40 \param ID[in] FIFO_MONITOR identifier 46 const fifo_monitor_ID_t ID, 49 /*! Read the state of FIFO_MONITOR[ID] 51 \param ID[in] FIFO_MONITOR identifier 54 \return none, state = FIFO_MONITOR[ID].state 57 const fifo_monitor_ID_t ID, 62 \param ID[in] FIFO_MONITOR identifier 69 const fifo_monitor_ID_t ID, [all...] |
H A D | sp_public.h | 22 /*! Enable or disable the program complete irq signal of SP[ID] 24 \param ID[in] SP identifier 27 \return none, if(cnd) enable(SP[ID].irq) else disable(SP[ID].irq) 30 const sp_ID_t ID, 33 /*! Write to the status and control register of SP[ID] 35 \param ID[in] SP identifier 39 \return none, SP[ID].sc[reg] = value 42 const sp_ID_t ID, 46 /*! Read from the status and control register of SP[ID] [all...] |
H A D | isp_public.h | 22 /*! Enable or disable the program complete irq signal of ISP[ID] 24 \param ID[in] SP identifier 27 \return none, if(cnd) enable(ISP[ID].irq) else disable(ISP[ID].irq) 30 const isp_ID_t ID, 33 /*! Write to the status and control register of ISP[ID] 35 \param ID[in] ISP identifier 39 \return none, ISP[ID].sc[reg] = value 42 const isp_ID_t ID, 46 /*! Read from the status and control register of ISP[ID] [all...] |
H A D | gdc_public.h | 19 /*! Write the bicubic interpolation table of GDC[ID] 21 \param ID[in] GDC identifier 35 \return none, GDC[ID].lut[0...3][0...HRT_GDC_N-1] = data 38 const gdc_ID_t ID, 41 /*! Convert the bicubic interpolation table of GDC[ID] to the ISP-specific format 43 \param ID[in] GDC identifier 51 /*! Return the integer representation of 1.0 of GDC[ID] 53 \param ID[in] GDC identifier 58 const gdc_ID_t ID);
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H A D | gpio_public.h | 21 /*! Write to a control register of GPIO[ID] 23 \param ID[in] GPIO identifier 27 \return none, GPIO[ID].ctrl[reg] = value 30 const gpio_ID_t ID, 34 /*! Read from a control register of GPIO[ID] 36 \param ID[in] GPIO identifier 40 \return GPIO[ID].ctrl[reg] 43 const gpio_ID_t ID,
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H A D | irq_public.h | 22 /*! Write to a control register of IRQ[ID] 24 \param ID[in] IRQ identifier 28 \return none, IRQ[ID].ctrl[reg] = value 31 const irq_ID_t ID, 35 /*! Read from a control register of IRQ[ID] 37 \param ID[in] IRQ identifier 41 \return IRQ[ID].ctrl[reg] 44 const irq_ID_t ID, 47 /*! Enable an IRQ channel of IRQ[ID] with a mode 49 \param ID[i [all...] |
H A D | hmem_public.h | 21 /*! Return the size of HMEM[ID] 23 \param ID[in] HMEM identifier 28 \return sizeof(HMEM[ID]) 31 const hmem_ID_t ID);
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H A D | gp_device_public.h | 23 /*! Read the state of GP_DEVICE[ID] 25 \param ID[in] GP_DEVICE identifier 28 \return none, state = GP_DEVICE[ID].state 31 const gp_device_ID_t ID, 34 /*! Write to a control register of GP_DEVICE[ID] 36 \param ID[in] GP_DEVICE identifier 40 \return none, GP_DEVICE[ID].ctrl[reg] = value 43 const gp_device_ID_t ID, 47 /*! Read from a control register of GP_DEVICE[ID] 49 \param ID[i [all...] |
H A D | dma_public.h | 21 /*! Write to a control register of DMA[ID] 23 \param ID[in] DMA identifier 27 \return none, DMA[ID].ctrl[reg] = value 30 const dma_ID_t ID, 34 /*! Read from a control register of DMA[ID] 36 \param ID[in] DMA identifier 40 \return DMA[ID].ctrl[reg] 43 const dma_ID_t ID, 46 /*! Set maximum burst size of DMA[ID] 48 \param ID[i [all...] |
H A D | isys_stream2mmio_public.h | 28 * @param[in] id The global unique ID of the steeam2mmio controller. 32 const stream2mmio_ID_t ID, 39 * @param[in] id The global unique ID of the steeam2mmio controller. 40 * @param[in] sid_id The sid ID. 44 const stream2mmio_ID_t ID, 58 * @param[in] ID The global unique ID for the stream2mmio-controller instance. 65 const stream2mmio_ID_t ID, 81 * @param[in] id The global unique ID of the st2mmio 85 const stream2mmio_ID_t ID, [all...] |
H A D | timed_ctrl_public.h | 21 /*! Write to a control register of TIMED_CTRL[ID] 23 \param ID[in] TIMED_CTRL identifier 27 \return none, TIMED_CTRL[ID].ctrl[reg] = value 30 const timed_ctrl_ID_t ID, 35 const timed_ctrl_ID_t ID, 43 const timed_ctrl_ID_t ID, 52 const timed_ctrl_ID_t ID,
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/linux-master/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/ |
H A D | input_formatter.c | 60 const input_formatter_ID_t ID) 65 assert(ID < N_INPUT_FORMATTER_ID); 67 addr = HIVE_IF_SRST_ADDRESS[ID]; 68 rst = HIVE_IF_SRST_MASK[ID]; 74 if (!HIVE_IF_BIN_COPY[ID]) { 75 input_formatter_reg_store(ID, addr, rst); 82 const input_formatter_ID_t ID) 84 assert(ID < N_INPUT_FORMATTER_ID); 86 return input_formatter_alignment[ID]; 90 const input_formatter_ID_t ID, 59 input_formatter_rst( const input_formatter_ID_t ID) argument 81 input_formatter_get_alignment( const input_formatter_ID_t ID) argument 89 input_formatter_set_fifo_blocking_mode( const input_formatter_ID_t ID, const bool enable) argument 103 input_formatter_get_switch_state( const input_formatter_ID_t ID, input_formatter_switch_state_t *state) argument 137 input_formatter_get_state( const input_formatter_ID_t ID, input_formatter_state_t *state) argument 218 input_formatter_bin_get_state( const input_formatter_ID_t ID, input_formatter_bin_state_t *state) argument [all...] |
H A D | gp_timer.c | 49 void gp_timer_init(gp_timer_ID_t ID) argument 55 gp_timer_reg_store(_REG_GP_TIMER_ENABLE_ID(ID), 1); 58 gp_timer_reg_store(_REG_GP_TIMER_SIGNAL_SELECT_ID(ID), GP_TIMER_SIGNAL_SELECT); 61 gp_timer_reg_store(_REG_GP_TIMER_COUNT_TYPE_ID(ID), GP_TIMER_COUNT_TYPE_LOW); 68 gp_timer_read(gp_timer_ID_t ID) argument 70 return gp_timer_reg_load(_REG_GP_TIMER_VALUE_ID(ID));
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H A D | fifo_monitor.c | 44 const fifo_monitor_ID_t ID, 49 const fifo_monitor_ID_t ID, 54 const fifo_monitor_ID_t ID, 63 state->src_valid = fifo_monitor_status_valid(ID, 66 state->fifo_accept = fifo_monitor_status_accept(ID, 69 state->fifo_valid = fifo_monitor_status_valid(ID, 72 state->sink_accept = fifo_monitor_status_accept(ID, 77 state->src_valid = fifo_monitor_status_valid(ID, 80 state->fifo_accept = fifo_monitor_status_accept(ID, 83 state->fifo_valid = fifo_monitor_status_valid(ID, 53 fifo_channel_get_state( const fifo_monitor_ID_t ID, const fifo_channel_t channel_id, fifo_channel_state_t *state) argument 508 fifo_switch_get_state( const fifo_monitor_ID_t ID, const fifo_switch_t switch_id, fifo_switch_state_t *state) argument 530 fifo_monitor_get_state( const fifo_monitor_ID_t ID, fifo_monitor_state_t *state) argument 552 fifo_monitor_status_valid( const fifo_monitor_ID_t ID, const unsigned int reg, const unsigned int port_id) argument 562 fifo_monitor_status_accept( const fifo_monitor_ID_t ID, const unsigned int reg, const unsigned int port_id) argument [all...] |
H A D | timed_ctrl.c | 25 const timed_ctrl_ID_t ID, 32 OP___assert(ID == TIMED_CTRL0_ID); 33 OP___assert(TIMED_CTRL_BASE[ID] != (hrt_address)-1); 35 timed_ctrl_reg_store(ID, _HRT_TIMED_CONTROLLER_CMD_REG_IDX, mask); 36 timed_ctrl_reg_store(ID, _HRT_TIMED_CONTROLLER_CMD_REG_IDX, condition); 37 timed_ctrl_reg_store(ID, _HRT_TIMED_CONTROLLER_CMD_REG_IDX, counter); 38 timed_ctrl_reg_store(ID, _HRT_TIMED_CONTROLLER_CMD_REG_IDX, (hrt_data)addr); 39 timed_ctrl_reg_store(ID, _HRT_TIMED_CONTROLLER_CMD_REG_IDX, value); 46 const timed_ctrl_ID_t ID, 57 timed_ctrl_snd_commnd(ID, mas 24 timed_ctrl_snd_commnd( const timed_ctrl_ID_t ID, hrt_data mask, hrt_data condition, hrt_data counter, hrt_address addr, hrt_data value) argument 45 timed_ctrl_snd_sp_commnd( const timed_ctrl_ID_t ID, hrt_data mask, hrt_data condition, hrt_data counter, const sp_ID_t SP_ID, hrt_address offset, hrt_data value) argument 61 timed_ctrl_snd_gpio_commnd( const timed_ctrl_ID_t ID, hrt_data mask, hrt_data condition, hrt_data counter, const gpio_ID_t GPIO_ID, hrt_address offset, hrt_data value) argument [all...] |
H A D | dma.c | 27 dma_set_max_burst_size(const dma_ID_t ID, dma_connection conn, argument 30 assert(ID < N_DMA_ID); 32 dma_reg_store(ID, DMA_DEV_INFO_REG_IDX(_DMA_DEV_INTERF_MAX_BURST_IDX, conn),
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H A D | gdc.c | 27 const gdc_ID_t ID, 39 const gdc_ID_t ID, 44 assert(ID < N_GDC_ID); 58 gdc_reg_store(ID, lut_offset++, word_0); 59 gdc_reg_store(ID, lut_offset++, word_1); 98 const gdc_ID_t ID) 100 assert(ID < N_GDC_ID); 101 (void)ID; 109 const gdc_ID_t ID, 113 ia_css_device_store_uint32(GDC_BASE[ID] 38 gdc_lut_store( const gdc_ID_t ID, const int data[4][HRT_GDC_N]) argument 97 gdc_get_unity( const gdc_ID_t ID) argument 108 gdc_reg_store( const gdc_ID_t ID, const unsigned int reg, const hrt_data value) argument [all...] |
H A D | vmem_local.h | 27 const isp_ID_t ID, 33 const isp_ID_t ID, 39 const isp_ID_t ID, 49 const isp_ID_t ID,
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H A D | input_system.c | 44 static void receiver_rst(const rx_ID_t ID); 45 static void input_system_network_rst(const input_system_ID_t ID); 48 const input_system_ID_t ID, 53 const input_system_ID_t ID, 58 const input_system_ID_t ID, 63 const input_system_ID_t ID, 82 static void gp_device_rst(const gp_device_ID_t ID); 84 static void input_selector_cfg_for_sensor(const gp_device_ID_t ID); 86 static void input_switch_rst(const gp_device_ID_t ID); 89 const gp_device_ID_t ID, 93 receiver_set_compression( const rx_ID_t ID, const unsigned int cfg_ID, const mipi_compressor_t comp, const mipi_predictor_t pred) argument 142 receiver_port_enable( const rx_ID_t ID, const enum mipi_port_id port_ID, const bool cnd) argument 160 is_receiver_port_enabled( const rx_ID_t ID, const enum mipi_port_id port_ID) argument 169 receiver_irq_enable( const rx_ID_t ID, const enum mipi_port_id port_ID, const rx_irq_info_t irq_info) argument 178 receiver_get_irq_info( const rx_ID_t ID, const enum mipi_port_id port_ID) argument 186 receiver_irq_clear( const rx_ID_t ID, const enum mipi_port_id port_ID, const rx_irq_info_t irq_info) argument 198 receiver_rst( const rx_ID_t ID) argument 214 gp_device_rst(const gp_device_ID_t ID) argument 261 input_selector_cfg_for_sensor(const gp_device_ID_t ID) argument 277 input_switch_rst(const gp_device_ID_t ID) argument 295 input_switch_cfg( const gp_device_ID_t ID, const input_switch_cfg_t *const cfg) argument 319 input_system_network_rst(const input_system_ID_t ID) argument 576 capture_unit_configure( const input_system_ID_t ID, const sub_system_ID_t sub_id, const isp2400_ib_buffer_t *const cfg) argument 600 acquisition_unit_configure( const input_system_ID_t ID, const sub_system_ID_t sub_id, const isp2400_ib_buffer_t *const cfg) argument 623 ctrl_unit_configure( const input_system_ID_t ID, const sub_system_ID_t sub_id, const ctrl_unit_cfg_t *const cfg) argument 689 input_system_network_configure( const input_system_ID_t ID, const input_system_network_cfg_t *const cfg) argument [all...] |
/linux-master/drivers/staging/media/atomisp/pci/css_2401_system/host/ |
H A D | isys_stream2mmio_private.h | 44 const stream2mmio_ID_t ID, 53 for (i = STREAM2MMIO_SID0_ID; i < N_STREAM2MMIO_SID_PROCS[ID]; i++) { 54 stream2mmio_get_sid_state(ID, i, &state->sid_state[i]); 63 const stream2mmio_ID_t ID, 68 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_ACKNOWLEDGE_REG_ID); 71 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_PIX_WIDTH_ID_REG_ID); 74 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_START_ADDR_REG_ID); 77 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_END_ADDR_REG_ID); 80 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_STRIDE_REG_ID); 83 stream2mmio_reg_load(ID, sid_i 43 stream2mmio_get_state( const stream2mmio_ID_t ID, stream2mmio_state_t *state) argument 62 stream2mmio_get_sid_state( const stream2mmio_ID_t ID, const stream2mmio_sid_ID_t sid_id, stream2mmio_sid_state_t *state) argument 109 stream2mmio_dump_state( const stream2mmio_ID_t ID, stream2mmio_state_t *state) argument 136 stream2mmio_reg_load( const stream2mmio_ID_t ID, const stream2mmio_sid_ID_t sid_id, const uint32_t reg_idx) argument [all...] |
/linux-master/drivers/scsi/aic7xxx/ |
H A D | aic7xxx_osm_pci.c | 47 #define ID(x) ID_C(x, PCI_CLASS_STORAGE_SCSI) macro 51 ID(ID_AHA_2902_04_10_15_20C_30C), 53 ID(ID_AHA_2930CU), 54 ID(ID_AHA_1480A & ID_DEV_VENDOR_MASK), 55 ID(ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK), 56 ID(ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK), 57 ID(ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK), 59 ID(ID_AHA_2940), 60 ID(ID_AHA_3940), 61 ID(ID_AHA_398 [all...] |
H A D | aiclib.h | 141 /* Macros for generating the elements of the PCI ID tables. */ 163 ID(x), \ 164 ID((x) | 0x0001000000000000ull), \ 165 ID((x) | 0x0002000000000000ull), \ 166 ID((x) | 0x0003000000000000ull), \ 167 ID((x) | 0x0004000000000000ull), \ 168 ID((x) | 0x0005000000000000ull), \ 169 ID((x) | 0x0006000000000000ull), \ 170 ID((x) | 0x0007000000000000ull), \ 171 ID(( [all...] |
/linux-master/drivers/char/agp/ |
H A D | via-agp.c | 506 #define ID(x) \ macro 515 ID(PCI_DEVICE_ID_VIA_82C597_0), 516 ID(PCI_DEVICE_ID_VIA_82C598_0), 517 ID(PCI_DEVICE_ID_VIA_8501_0), 518 ID(PCI_DEVICE_ID_VIA_8601_0), 519 ID(PCI_DEVICE_ID_VIA_82C691_0), 520 ID(PCI_DEVICE_ID_VIA_8371_0), 521 ID(PCI_DEVICE_ID_VIA_8633_0), 522 ID(PCI_DEVICE_ID_VIA_XN266), 523 ID(PCI_DEVICE_ID_VIA_836 [all...] |
/linux-master/drivers/staging/media/atomisp/pci/ |
H A D | isp2400_input_system_public.h | 21 /*! Set compression parameters for cfg[cfg_ID] of RECEIVER[ID] 23 \param ID[in] RECEIVER identifier 32 \return none, RECEIVER[ID].cfg[cfg_ID] = {comp, pred} 35 const rx_ID_t ID, 40 /*! Enable PORT[port_ID] of RECEIVER[ID] 42 \param ID[in] RECEIVER identifier 46 \return None, enable(RECEIVER[ID].PORT[port_ID]) 49 const rx_ID_t ID, 53 /*! Flag if PORT[port_ID] of RECEIVER[ID] is enabled 55 \param ID[i [all...] |