Searched refs:CLK_NR_CLKS (Results 26 - 50 of 55) sorted by relevance

123

/linux-master/include/dt-bindings/clock/
H A Drk3328-cru.h204 #define CLK_NR_CLKS (HCLK_HDCP + 1) macro
H A Drk3308-cru.h215 #define CLK_NR_CLKS (PCLK_OWIRE + 1) macro
H A Dpx30-cru.h178 #define CLK_NR_CLKS (PCLK_OTP_PHY + 1) macro
H A Drk3368-cru.h185 #define CLK_NR_CLKS (HCLK_PERI + 1) macro
H A Drockchip,rv1126-cru.h356 #define CLK_NR_CLKS (PCLK_OTP + 1) macro
H A Drk3399-cru.h338 #define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1) macro
H A Drk3568-cru.h486 #define CLK_NR_CLKS (PCLK_CORE_PVTM + 1) macro
/linux-master/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Drk3308-cru.h215 #define CLK_NR_CLKS (PCLK_OWIRE + 1) macro
H A Dpx30-cru.h178 #define CLK_NR_CLKS (PCLK_OTP_PHY + 1) macro
H A Drk3368-cru.h185 #define CLK_NR_CLKS (HCLK_PERI + 1) macro
H A Drockchip,rv1126-cru.h356 #define CLK_NR_CLKS (PCLK_OTP + 1) macro
H A Drk3399-cru.h338 #define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1) macro
H A Drk3568-cru.h486 #define CLK_NR_CLKS (PCLK_CORE_PVTM + 1) macro
/linux-master/drivers/clk/rockchip/
H A Dclk-rk3036.c455 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
H A Dclk-rk3228.c694 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
H A Dclk-rk3128.c582 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
H A Dclk-rk3188.c771 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
H A Dclk-px30.c1013 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
H A Dclk-rk3288.c942 ctx = rockchip_clk_init(np, rk3288_cru_base, CLK_NR_CLKS);
H A Dclk-rk3368.c877 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
H A Dclk-rk3328.c892 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
H A Dclk-rv1108.c796 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
/linux-master/drivers/clk/pistachio/
H A Dclk-pistachio.c175 p = pistachio_clk_alloc_provider(np, CLK_NR_CLKS);
/linux-master/drivers/clk/actions/
H A Dowl-s500.c529 .num = CLK_NR_CLKS,
H A Dowl-s700.c574 .num = CLK_NR_CLKS,

Completed in 392 milliseconds

123