/linux-master/drivers/staging/rtl8723bs/hal/ |
H A D | odm_DynamicBBPowerSaving.c | 38 pDM_PSTable->RegC70 = (PHY_QueryBBReg(pDM_Odm->Adapter, 0xc70, bMaskDWord)&BIT3)>>3; 66 PHY_SetBBReg(pDM_Odm->Adapter, 0xc70, BIT3, 0); /* RegC70[3]= 1'b0 */ 74 PHY_SetBBReg(pDM_Odm->Adapter, 0xc70, BIT3, pDM_PSTable->RegC70);
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H A D | HalBtc8723b2Ant.h | 12 #define BT_INFO_8723B_2ANT_B_ACL_BUSY BIT3
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H A D | HalHWImg8723B_MAC.c | 17 ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA */ 62 if ((cond1 & BIT3) != 0) /* APA */
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H A D | HalBtc8723b1Ant.h | 12 #define BT_INFO_8723B_1ANT_B_ACL_BUSY BIT3
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H A D | HalHWImg8723B_RF.c | 17 ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA */ 68 if ((cond1 & BIT3) != 0) /* APA */
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H A D | HalHWImg8723B_BB.c | 17 ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA */ 63 if ((cond1 & BIT3) != 0) /* APA */
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H A D | odm.h | 368 ODM_BB_FA_CNT = BIT3, 446 ODM_WM_N24G = BIT3, 751 /* Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */
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/linux-master/drivers/net/wireless/realtek/rtlwifi/btcoexist/ |
H A D | halbt_precomp.h | 34 #define BIT3 0x00000008 macro
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H A D | halbtc8821a2ant.h | 12 #define BT_INFO_8821A_2ANT_B_ACL_BUSY BIT3
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H A D | halbtc8723b1ant.h | 11 #define BT_INFO_8723B_1ANT_B_ACL_BUSY BIT3
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H A D | halbtc8723b2ant.h | 14 #define BT_INFO_8723B_2ANT_B_ACL_BUSY BIT3
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H A D | halbtc8821a1ant.h | 12 #define BT_INFO_8821A_1ANT_B_ACL_BUSY BIT3
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H A D | halbtc8192e2ant.h | 11 #define BT_INFO_8192E_2ANT_B_ACL_BUSY BIT3
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H A D | halbtcoutsrc.h | 95 #define ALGO_TRACE BIT3 107 #define WIFI_P2P_GO_CONNECTED BIT3
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/linux-master/drivers/staging/rtl8723bs/include/ |
H A D | hal_pwr_seq.h | 48 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0},/* disable SW LPS 0x04[10]= 0 and WLSUS_EN 0x04[11]= 0*/ \ 54 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \ 63 {0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3},/*For GPIO9 internal pull high setting by test chip*/\ 83 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ 84 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ 87 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT [all...] |
H A D | rtw_ht.h | 67 #define LDPC_HT_CAP_TX BIT3 72 #define STBC_HT_CAP_TX BIT3
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H A D | rtl8723b_spec.h | 211 #define IMR_VIDOK_8723B BIT3 /* AC_VI DMA OK */
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H A D | osdep_service.h | 20 #define BIT3 0x00000008 macro
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H A D | hal_com_reg.h | 550 #define RRSR_11M BIT3 575 #define HAL92C_WOL_DEAUTH_EVENT BIT3 673 #define WOW_UWF BIT3 /* Unicast Wakeup frame. */ 712 #define IMR_BEDOK BIT3 /* AC_BE DMA OK Interrupt */ 760 #define RCR_AB BIT3 /* Accept broadcast packet */ 1281 #define SDIO_HIMR_RXERR_MSK BIT3 1303 #define SDIO_HISR_RXERR BIT3 1376 #define WL_HWROF_EN BIT3 /* Enable GPIO[9] as WiFi RF HW PDn source */
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/linux-master/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/ |
H A D | pwrseq.h | 35 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \ 105 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3 \ 110 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \ 176 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3 \ 202 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \ 386 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0 \ 404 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0 \ 475 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT [all...] |
/linux-master/drivers/scsi/ |
H A D | dc395x.h | 73 #define BIT3 0x00000008 macro 82 #define UNIT_RETRY BIT3 132 #define UNDER_RUN BIT3 168 #define WIDE_NEGO_DONE BIT3 595 #define ACTIVE_NEGATION BIT3
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/linux-master/drivers/video/fbdev/via/ |
H A D | dvi.c | 345 BIT0 + BIT1 + BIT2 + BIT3); 370 BIT0 + BIT1 + BIT2 + BIT3); 377 BIT0 + BIT1 + BIT2 + BIT3); 456 viafb_write_reg_mask(CRD2, VIACR, 0, BIT3);
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H A D | lcd.c | 420 viafb_write_reg_mask(CRA2, VIACR, 0x08, BIT3); 432 viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT3); 520 BIT0 + BIT1 + BIT2 + BIT3); 615 viafb_write_reg_mask(CR6A, VIACR, 0, BIT3); 663 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3); 758 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3); 759 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
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H A D | share.h | 17 #define BIT3 0x08 macro
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/linux-master/include/uapi/linux/ |
H A D | synclink.h | 22 #define BIT3 0x0008 macro
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