Searched refs:BIT0 (Results 26 - 50 of 52) sorted by relevance

123

/linux-master/drivers/video/fbdev/via/
H A Dshare.h14 #define BIT0 0x01 macro
H A Dhw.c472 viafb_write_reg_mask(CR47, VIACR, 0, BIT0);
949 viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
950 /*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */
986 reg_mask = reg_mask | (BIT0 << j);
987 get_bit = (timing_value & (BIT0 << bit_num));
1667 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
1681 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
1688 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
/linux-master/drivers/staging/rtl8723bs/include/
H A Drtw_pwrctrl.h124 #define RT_PCI_ASPM_OSC_ENABLE BIT0 /* PCI ASPM controlled by OS according to ACPI Spec 5.0 */
H A Dhal_data.h80 #define DYNAMIC_FUNC_BT BIT0
H A Drtw_cmd.h36 RTW_CMDF_DIRECTLY = BIT0,
H A Dhal_intf.h12 RTW_PCIE = BIT0,
H A Drtw_mlme.h279 RTW_ROAM_ON_EXPIRED = BIT0,
H A Ddrv_types.h118 /* BIT0 - 20MHz, 1: support, 0: non-support */
123 /* BIT0: Enable VHT LDPC Rx, BIT1: Enable VHT LDPC Tx, BIT4: Enable HT LDPC Rx, BIT5: Enable HT LDPC Tx */
125 /* BIT0: Enable VHT STBC Rx, BIT1: Enable VHT STBC Tx, BIT4: Enable HT STBC Rx, BIT5: Enable HT STBC Tx */
127 /* BIT0: Enable VHT Beamformer, BIT1: Enable VHT Beamformee, BIT4: Enable HT Beamformer, BIT5: Enable HT Beamformee */
451 #define DF_TX_BIT BIT0
H A Drtw_mlme_ext.h44 #define DYNAMIC_BB_DIG BIT0 /* ODM_BB_DIG */
/linux-master/drivers/staging/rtl8723bs/hal/
H A DHalHWImg8723B_MAC.c56 if ((cond1 & BIT0) != 0) /* GLNA */
H A Dodm.h365 ODM_BB_DIG = BIT0,
424 /* For example 1T2R (A+AB = BIT0|BIT4|BIT5) */
444 ODM_WM_B = BIT0,
751 /* Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */
H A DHal8723BReg.h403 #define IMR_ROK_8723B BIT0 /* Receive DMA OK */
H A DHalHWImg8723B_RF.c62 if ((cond1 & BIT0) != 0) /* GLNA */
H A DHalBtcOutSrc.h72 #define WIFI_STA_CONNECTED BIT0
H A DHalBtc8723b1Ant.c248 H2C_Parameter[0] |= BIT0; /* trigger */
605 H2C_Parameter[1] |= BIT0;
742 H2C_Parameter[0] |= BIT0; /* function enable */
873 if (u1Tmp & BIT0)
2148 pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x2, u2Tmp | BIT0 | BIT1);
2158 /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */
H A DHalBtc8723b2Ant.c188 H2C_Parameter[0] |= BIT0; /* trigger */
513 H2C_Parameter[1] |= BIT0;
752 H2C_Parameter[0] |= BIT0; /* function enable */
2340 pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x2, u2Tmp | BIT0 | BIT1);
2350 /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */
H A DHalHWImg8723B_BB.c57 if ((cond1 & BIT0) != 0) /* GLNA */
H A Drtl8723b_phycfg.c394 rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal|BIT13|BIT0|BIT1));
/linux-master/lib/zstd/common/
H A Dzstd_internal.h71 #define BIT0 1 macro
/linux-master/drivers/net/wireless/realtek/rtlwifi/btcoexist/
H A Dhalbtc8192e2ant.c419 h2c_parameter[0] |= BIT0; /* trigger */
786 h2c_parameter[0] |= BIT0;
1114 h2c_parameter[0] |= BIT0; /* function enable */
2641 u8tmp |= BIT0;
2645 u8tmp |= BIT0;
2758 (bt_info_ext&BIT0) ? "Basic rate" : "EDR rate");
H A Dhalbtc8821a1ant.c398 h2c_parameter[0] |= BIT0; /* trigger */
655 h2c_parameter[1] |= BIT0;
787 h2c_parameter[0] |= BIT0; /* function enable */
2208 (bt_info_ext & BIT0) ?
H A Dhalbtc8723b2ant.c335 h2c_parameter[0] |= BIT0; /* trigger */
754 h2c_parameter[1] |= BIT0;
992 h2c_parameter[0] |= BIT0; /* function enable */
3571 btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT0 | BIT1);
3602 * BIT0: "0" : no antenna inverse; "1" : antenna inverse
3725 (bt_info_ext & BIT0) ? "Basic rate" : "EDR rate");
H A Dhalbtc8821a2ant.c331 h2c_parameter[0] |= BIT0; /* trigger */
711 h2c_parameter[1] |= BIT0;
968 h2c_parameter[0] |= BIT0; /* function enable */
3586 * BIT0: "0" for no antenna inverse; "1" for antenna inverse
3711 (bt_info_ext&BIT0) ? "Basic rate" : "EDR rate");
H A Dhalbtc8723b1ant.c463 h2c_parameter[1] |= BIT0;
637 h2c_parameter[0] |= BIT0; /* function enable */
2374 btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT0 | BIT1);
2385 * BIT0: "0" for no antenna inverse; "1" for antenna inverse
2562 (bt_info_ext & BIT0) ? "Basic rate" : "EDR rate");
/linux-master/drivers/net/wireless/realtek/rtlwifi/rtl8192d/
H A Dreg.h503 #define WOW_PMEN BIT0 /* Power management Enable. */

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