/linux-master/drivers/staging/rtl8723bs/include/ |
H A D | hal_pwr_seq.h | 44 {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \ 49 {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* Disable USB suspend */ \ 51 {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* Enable USB suspend */ \ 52 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]= 1*/ \ 55 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \ 56 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, [all...] |
H A D | rtw_ht.h | 64 #define LDPC_HT_ENABLE_RX BIT0 69 #define STBC_HT_ENABLE_RX BIT0 74 #define BEAMFORMING_HT_BEAMFORMER_ENABLE BIT0 /* Declare our NIC supports beamformer */
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H A D | hal_phy.h | 13 #define ANT_DETECT_BY_SINGLE_TONE BIT0
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H A D | hal_com_reg.h | 524 #define HSISR_GPIO12_0_INT BIT0 547 #define RRSR_1M BIT0 572 #define HAL92C_WOL_PTK_UPDATE_EVENT BIT0 670 #define WOW_PMEN BIT0 /* Power management Enable. */ 715 #define IMR_ROK BIT0 /* Receive DMA OK Interrupt */ 726 #define IMR_WLANOFF BIT0 763 #define RCR_AAP BIT0 /* Accept all unicast packet */ 1278 #define SDIO_HIMR_RX_REQUEST_MSK BIT0 1300 #define SDIO_HISR_RX_REQUEST BIT0 1338 #define HCI_SUS_CTRL BIT0 [all...] |
H A D | rtl8723b_spec.h | 214 #define IMR_ROK_8723B BIT0 /* Receive DMA OK */
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H A D | osdep_service.h | 17 #define BIT0 0x00000001 macro
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/linux-master/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/ |
H A D | pwrseq.h | 38 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \ 41 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0}, 51 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \ 96 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \ 155 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \ 181 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \ 247 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \ 294 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT [all...] |
/linux-master/drivers/video/fbdev/via/ |
H A D | dvi.c | 45 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); 52 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); 335 BIT0 + BIT1 + BIT2); 338 BIT0 + BIT1 + BIT2); 345 BIT0 + BIT1 + BIT2 + BIT3); 363 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1); 370 BIT0 + BIT1 + BIT2 + BIT3); 377 BIT0 + BIT1 + BIT2 + BIT3); 395 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0); 396 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 [all...] |
H A D | via_utility.c | 152 viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0); 169 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0); 207 viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0);
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H A D | lcd.c | 345 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2); 520 BIT0 + BIT1 + BIT2 + BIT3); 561 BIT0 + BIT1 + BIT2); 583 viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0); 650 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1); 652 viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1); 659 viafb_write_reg_mask(CR91, VIACR, 0, BIT0); 668 viafb_write_reg_mask(CRD3, VIACR, 0, BIT0); 744 BIT7 + BIT2 + BIT1 + BIT0); 844 bdithering = BIT0; [all...] |
/linux-master/drivers/scsi/ |
H A D | dc395x.h | 76 #define BIT0 0x00000001 macro 79 #define UNIT_ALLOCATED BIT0 85 #define DASD_SUPPORT BIT0 121 #define RESET_DEV BIT0 126 #define ABORT_DEV_ BIT0 129 #define SRB_OK BIT0 143 #define AUTO_REQSENSE BIT0 165 #define SYNC_NEGO_ENABLE BIT0 592 #define MORE2_DRV BIT0
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/linux-master/drivers/net/wireless/realtek/rtlwifi/btcoexist/ |
H A D | halbt_precomp.h | 31 #define BIT0 0x00000001 macro
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H A D | halbtc8723b1ant.h | 14 #define BT_INFO_8723B_1ANT_B_CONNECTION BIT0 17 (((_BT_INFO_EXT_&BIT0)) ? true : false)
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H A D | halbtc8821a1ant.h | 15 #define BT_INFO_8821A_1ANT_B_CONNECTION BIT0 18 (((_BT_INFO_EXT_&BIT0)) ? true : false)
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H A D | halbtc8821a2ant.h | 15 #define BT_INFO_8821A_2ANT_B_CONNECTION BIT0
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H A D | halbtc8723b2ant.h | 17 #define BT_INFO_8723B_2ANT_B_CONNECTION BIT0
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H A D | halbtc8192e2ant.h | 14 #define BT_INFO_8192E_2ANT_B_CONNECTION BIT0
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H A D | halbtcoutsrc.h | 88 #define INTF_INIT BIT0 92 #define ALGO_BT_RSSI_STATE BIT0 104 #define WIFI_STA_CONNECTED BIT0
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/linux-master/drivers/staging/rtl8723bs/hal/ |
H A D | odm_reg.h | 89 #define BIT_FA_RESET BIT0
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H A D | HalBtc8723b1Ant.h | 15 #define BT_INFO_8723B_1ANT_B_CONNECTION BIT0 18 (((_BT_INFO_EXT_ & BIT0)) ? true : false)
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H A D | HalBtc8723b2Ant.h | 15 #define BT_INFO_8723B_2ANT_B_CONNECTION BIT0
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H A D | odm_DIG.h | 81 ODM_PAUSE_DIG = BIT0,
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H A D | odm_HWConfig.c | 338 pEntry->rssi_stat.PacketMap = (pEntry->rssi_stat.PacketMap<<1) | BIT0; 372 OFDM_pkt += (u8)(pEntry->rssi_stat.PacketMap>>i)&BIT0;
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/linux-master/drivers/tty/ |
H A D | synclink_gt.c | 186 #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0)) 193 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0) 351 #define MASK_FRAMING BIT0 393 #define IRQ_MASTER BIT0 1781 status = *(p + 1) & (BIT1 + BIT0); 1785 else if (status & BIT0) 1792 else if (status & BIT0) 2005 if (status & BIT0) { 3778 if (!(rd_reg32(info, RDCSR) & BIT0)) [all...] |
/linux-master/include/uapi/linux/ |
H A D | synclink.h | 19 #define BIT0 0x0001 macro
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