Searched refs:si (Results 151 - 175 of 242) sorted by relevance

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/haiku/src/add-ons/accelerants/radeon/
H A Dmonitor_detection.c159 old_vclk_ecp_cntl = Radeon_INPLL(ai->regs, ai->si->asic,
164 Radeon_OUTPLL(ai->regs, ai->si->asic, RADEON_VCLK_ECP_CNTL, value);
169 Radeon_OUTPLL(ai->regs, ai->si->asic, RADEON_VCLK_ECP_CNTL,
293 if (ai->si->is_mobility)
296 switch (ai->si->asic) {
508 Radeon_VIPWrite(ai, ai->si->theatre_channel, THEATRE_VIP_TV_DAC_CNTL,
512 Radeon_VIPRead(ai, ai->si->theatre_channel, THEATRE_VIP_TV_DAC_CNTL, &tmp);
524 Radeon_VIPWrite(ai, ai->si->theatre_channel, THEATRE_VIP_TV_DAC_CNTL,
527 Radeon_VIPWrite(ai, ai->si->theatre_channel, THEATRE_VIP_TV_DAC_CNTL,
530 Radeon_VIPRead(ai, ai->si
909 shared_info *si = ai->si; local
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H A DAcceleration.c56 ++ai->si->engine.count;
104 ++ai->si->engine.count;
148 ++ai->si->engine.count;
182 ++ai->si->engine.count;
238 ++ai->si->engine.count;
265 ++ai->si->engine.count;
311 ++ai->si->engine.count;
336 if ( ai->si->asic >= rt_rv200 ) {
357 ++ai->si->engine.count;
364 if ( ai->si
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H A DProposeDisplayMode.c144 Radeon_ProposeDisplayMode(shared_info *si, crtc_info *crtc, argument
155 fp_info *flatpanel = &si->flatpanels[crtc->flatpanel_port];
157 SHOW_FLOW( 4, "CRTC %d, DVI %d", (crtc == &si->crtc[0]) ? 0 : 1, crtc->flatpanel_port );
393 if ((row_bytes * target->virtual_height) > si->memory[mt_local].size - 1024 )
394 target->virtual_height = (si->memory[mt_local].size - 1024) / row_bytes;
418 return ai->si->mode_count;
425 memcpy( dm, ai->mode_list, ai->si->mode_count * sizeof(display_mode) );
442 shared_info *si = ai->si; local
450 for( i = 0; i < si
541 shared_info *si = ai->si; local
631 shared_info *si = ai->si; local
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H A DCP.c52 CP_info *cp = &ai->si->cp;
73 LOG1( si->log, _GetAvailRingBufferQueue, space );
85 CP_info *cp = &ai->si->cp;
88 //ai->si->cp.scratch.ptr[1];
128 CP_info *cp = &ai->si->cp;
171 CP_info *cp = &ai->si->cp;
203 CP_info *cp = &ai->si->cp;
271 CP_info *cp = &ai->si->cp;
338 //(void)*(volatile int *)si->framebuffer;
363 CP_info *cp = &ai->si
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H A DCP.h67 return (uint32 *)(ai->mapped_memory[ai->si->cp.buffers.mem_type].data + ai->si->cp.buffers.mem_offset)
/haiku/src/add-ons/accelerants/matrox/
H A DGetAccelerantHook.c33 #define HRDC(x) case B_##x: return si->settings.hardcursor? (void *)x: (void *)0; // apsed
173 if (si->ps.card_type >= G200)
221 if (si->acc_mode)
226 ((si->fbc.bytes_per_row * si->dm.virtual_height) > (16 * 1024 * 1024)))
/haiku/src/add-ons/accelerants/matrox/engine/
H A Dmga_crtc2.c19 if ((!(target.flags & TV_BITS)) || (si->ps.card_type <= G400MAX))
59 if ((si->ps.secondary_head) && (!(target.flags & TV_BITS)))
166 if (si->ps.card_type <= G400MAX)
184 if (si->ps.secondary_head) gx00_maven_dpms(display, h, v);
206 if (si->crossed_conns)
277 offset = si->fbc.bytes_per_row;
278 if (si->interlaced_tv_mode)
299 LOG(2,("CRTC2: frameRAM: $%x\n",si->framebuffer));
300 LOG(2,("CRTC2: framebuffer: $%x\n",si->fbc.frame_buffer));
302 if (si
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H A Dmga_maventv.c52 switch (si->ps.card_type)
78 max_pclks_field = (si->ps.max_dac2_clock_16 * 1000000) / fields_sec;
81 max_pclks_field = (si->ps.max_dac2_clock_32 * 1000000) / fields_sec;
85 max_pclks_field = (si->ps.max_dac2_clock_32 * 1000000) / fields_sec;
90 max_pclks_field = (si->ps.max_dac2_clock_32dh * 1000000) / fields_sec;
106 if (req_pclks_field < (((si->ps.min_video_vco * 1000000) / fields_sec) / 8.0))
108 req_pclks_field = (((si->ps.min_video_vco * 1000000) / fields_sec) / 8.0);
125 if ((vco_clks_field >= ((si->ps.min_video_vco * 1000000) / fields_sec)) &&
126 (vco_clks_field <= ((si->ps.max_video_vco * 1000000) / fields_sec)))
132 n = (int)(((vco_clks_field * m) / ((si
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/haiku/src/add-ons/accelerants/neomagic/engine/
H A Dnm_crtc.c32 if (*hd_e > si->ps.max_crtc_width) *hd_e = si->ps.max_crtc_width;
52 if (si->ps.card_type < NM2200)
69 if (*vd_e > si->ps.max_crtc_height) *vd_e = si->ps.max_crtc_height;
114 * the display_mode as placed in si->dm may _not_ be modified!) */
117 if (target.timing.h_display > si->ps.panel_width)
119 target.timing.h_display = si->ps.panel_width;
123 if (target.timing.v_display > si->ps.panel_height)
125 target.timing.v_display = si
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/haiku/src/add-ons/accelerants/via/engine/
H A Dcrtc.c112 if (0)//si->ps.tmds1_active)
118 ((uint16)((si->ps.p1_timing.h_sync_start / ((float)si->ps.p1_timing.h_display)) *
122 ((uint16)((si->ps.p1_timing.h_sync_end / ((float)si->ps.p1_timing.h_display)) *
126 (((uint16)((si->ps.p1_timing.h_total / ((float)si->ps.p1_timing.h_display)) *
131 if (target.timing.h_display == si->ps.p1_timing.h_display)
134 if (si->ps.card_type == NV11)
148 ((uint16)((si
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/haiku/src/add-ons/kernel/drivers/graphics/intel_810/
H A Ddriver.cpp263 SharedInfo& si = *(di.sharedInfo);
264 memset(&si, 0, sharedSize);
265 si.regsArea = -1; // indicate area has not yet been created
266 si.videoMemArea = -1;
270 si.vendorID = pciInfo.vendor_id;
271 si.deviceID = pciInfo.device_id;
272 si.revision = pciInfo.revision;
273 strcpy(si.chipName, di.pChipInfo->chipName);
285 si.regsArea = map_physical_memory("i810 mmio registers",
292 if (si
367 SharedInfo& si = *(di.sharedInfo); local
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/haiku/src/add-ons/accelerants/ati/
H A Dmach64_mode.cpp25 SharedInfo& si = *gInfo.sharedInfo; local
26 M64_Params& params = si.m64Params;
38 if (si.chipType >= MACH64_264VTB) {
125 if (si.chipType >= MACH64_264VTB) {
156 SharedInfo& si = *gInfo.sharedInfo; local
157 M64_Params& params = si.m64Params;
230 SharedInfo& si = *gInfo.sharedInfo; local
289 if (si.chipType < MACH64_264VTB)
326 SharedInfo& si = *gInfo.sharedInfo; local
328 if (si
377 SharedInfo& si = *gInfo.sharedInfo; local
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H A Drage128_dpms.cpp58 SharedInfo& si = *gInfo.sharedInfo; local
60 TRACE("Rage128_SetDPMSMode() mode: %d, display type: %d\n", dpmsMode, si.displayType);
94 if (si.displayType == MT_LAPTOP) {
H A Drage128_overlay.cpp31 SharedInfo& si = *gInfo.sharedInfo; local
42 switch (si.displayMode.bitsPerPixel) {
97 if (si.displayMode.timing.pixel_clock < 125000)
99 else if (si.displayMode.timing.pixel_clock < 250000)
134 uint32 offset = (uint32)((addr_t)buffer->buffer - si.videoMemAddr);
/haiku/src/add-ons/kernel/drivers/graphics/radeon/
H A Dvip.c85 ACQUIRE_BEN( di->si->cp.lock );
90 RELEASE_BEN( di->si->cp.lock );
176 ACQUIRE_BEN( di->si->cp.lock );
181 RELEASE_BEN( di->si->cp.lock );
216 ACQUIRE_BEN( di->si->cp.lock );
221 RELEASE_BEN( di->si->cp.lock );
280 ACQUIRE_BEN( di->si->cp.lock );
286 RELEASE_BEN( di->si->cp.lock );
299 ACQUIRE_BEN( di->si->cp.lock );
339 RELEASE_BEN( di->si
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H A DCP_setup.c62 #define MEM2GC( mem ) ((mem).offset + si->memory[(mem).memory_type].virtual_addr_start)
83 mem_type = di->si->nonlocal_type; \
89 ((uint8 *)(memory_type == mt_local ? di->si->local_mem : \
96 (di->si->memory[(memory_type)].virtual_addr_start + (offset))
102 di->memmgr[ mem_type == mt_nonlocal ? di->si->nonlocal_type : mem_type], \
122 ACQUIRE_BEN( di->si->cp.lock );
134 RELEASE_BEN( di->si->cp.lock );
152 LOG( di->si->log, _Radeon_WaitForIdle );
175 LOG( di->si->log, _Radeon_WaitForFifo );
199 LOG( di->si
209 shared_info *si = di->si; local
324 shared_info *si = di->si; local
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/haiku/src/add-ons/accelerants/neomagic/
H A DProposeDisplayMode.c141 if ((si->ps.card_type == NM2070) && (target->space == B_RGB24_LITTLE))
246 if (si->settings.hardcursor) pointer_reservation = si->ps.curmem_size;
249 ((si->ps.memory_size * 1024) - pointer_reservation))
252 ((si->ps.memory_size * 1024) - pointer_reservation) / row_bytes;
302 if (si->settings.hardcursor)
306 if (si->ps.card_type > NM2070)
326 LOG(1, ("ACCELERANT_MODE_COUNT: the modelist contains %d modes\n",si->mode_count));
328 return si->mode_count;
336 memcpy(dm, my_mode_list, si
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H A DGetAccelerantHook.c32 #define HRDC(x) case B_##x: return si->settings.hardcursor? (void *)x: (void *)0;
172 if (si->ps.card_type > NM2070)
216 if (si->acc_mode)
/haiku/src/add-ons/accelerants/skeleton/engine/
H A Dagp.c24 // if (si->settings.unhide_fw)
72 if ((nai.agpi.device_id == si->device_id) &&
73 (nai.agpi.vendor_id == si->vendor_id) &&
74 (nai.agpi.bus == si->bus) &&
75 (nai.agpi.device == si->device) &&
76 (nai.agpi.function == si->function))
105 if (si->settings.force_pci)
/haiku/headers/private/kernel/arch/x86/32/
H A Diframe.h19 uint32 si; member in struct:iframe
/haiku/src/add-ons/accelerants/s3/
H A Dsavage_edid.cpp57 SharedInfo& si = *gInfo.sharedInfo; local
61 switch (si.chipType) {
/haiku/src/add-ons/media/media-add-ons/radeon/
H A DI2CPort.cpp19 si(NULL)
29 si = fRadeon.GetSharedInfo();
31 if ( si->asic == rt_rv200 ) {
78 if ( si == NULL )
81 if ( si->has_no_i2c ) {
162 if (si->asic >= rt_r200) {
200 if (si->asic >= rt_r200) {
/haiku/src/system/boot/platform/bios_ia32/
H A Dshell.S108 * %ax, %cx, %dx, %bp, %di and %si will be clobbered.
127 mov %cx, %si // and remember it
135 cmp %si, %ax
137 mov %si, %ax
169 mov $DOT_STRING, %si
186 mov %si, %ax // compare the sectors, not the cylinders
190 sub %si, %cx
206 mov $FAILURE_STRING, %si
/haiku/src/add-ons/accelerants/3dfx/
H A D3dfx_mode.cpp208 SharedInfo& si = *gInfo.sharedInfo; local
209 bool clock2X = mode.timing.pixel_clock > si.maxPixelClock / 2;
314 if (si.chipType == BANSHEE && pllFreq == 45831
340 OUTREG32(HW_CURSOR_PAT_ADDR, si.cursorOffset);
342 OUTREG32(VIDEO_DESKTOP_START_ADDR, si.frameBufferOffset);
350 OUTREG32(SRC_BASE_ADDR, si.frameBufferOffset);
351 OUTREG32(DST_BASE_ADDR, si.frameBufferOffset);
366 SharedInfo& si = *gInfo.sharedInfo; local
372 address += si.frameBufferOffset;
/haiku/headers/private/graphics/radeon/
H A Dradeon_interface.h82 // previously defined types, see si->nonlocal_type)
222 (ai->si->asic == rt_rv100) || \
223 (ai->si->asic == rt_rv200) || \
224 (ai->si->asic == rt_rs100) || \
225 (ai->si->asic == rt_rs200) || \
226 (ai->si->asic == rt_rv250) || \
227 (ai->si->asic == rt_rv280) || \
228 (ai->si->asic == rt_rs300))
238 (ai->si->asic == rt_r300) || \
239 (ai->si
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