/fuchsia/zircon/system/dev/board/vim/ |
H A D | vim-clk.c | 15 .base = S912_HIU_BASE,
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/fuchsia/zircon/system/dev/display/simple/ |
H A D | simple-bochs.c | 22 #define bochs_vbe_dispi_read(base, reg) pcie_read16(base + (0x500 + (reg << 1))) 23 #define bochs_vbe_dispi_write(base, reg, val) pcie_write16(base + (0x500 + (reg << 1)), val)
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/fuchsia/zircon/system/ulib/hwreg/include/hwreg/ |
H A D | mmio.h | 21 // |base()|. 30 // |base()|. 38 uintptr_t base() const { return mmio_; } function in class:hwreg::RegisterIo
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/fuchsia/zircon/system/ulib/zx/include/lib/zx/ |
H A D | resource.h | 31 uint64_t base,
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/fuchsia/zircon/third_party/ulib/jemalloc/include/jemalloc/internal/ |
H A D | stats_structs.h | 94 size_t base; member in struct:arena_stats_s
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/fuchsia/zircon/third_party/ulib/musl/src/misc/ |
H A D | nftw.c | 14 int base; member in struct:history 60 new.base = l + 1; 63 lev.base = h ? h->base : (name = strrchr(path, '/')) ? name - path : 0;
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/fuchsia/zircon/third_party/ulib/uboringssl/include/openssl/ |
H A D | crypto.h | 18 #include <openssl/base.h> 93 // base.h. 97 // OPENSSL_VERSION_NUMBER from base.h.
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H A D | hkdf.h | 18 #include <openssl/base.h>
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/fuchsia/zircon/kernel/dev/pcie/ |
H A D | pci_config.cpp | 61 * of PciConfig should only have the base interface available 67 PciPioConfig(uintptr_t base) argument 68 : PciConfig(base, PciAddrSpace::PIO) {} 113 PciMmioConfig(uintptr_t base) argument 114 : PciConfig(base, PciAddrSpace::MMIO) {} 159 fbl::RefPtr<PciConfig> PciConfig::Create(uintptr_t base, PciAddrSpace addr_type) { argument 163 LTRACEF("base %#" PRIxPTR ", type %s\n", base, (addr_type == PciAddrSpace::PIO) ? "PIO" : "MIO"); 166 cfg = fbl::AdoptRef(new (&ac) PciPioConfig(base)); 168 cfg = fbl::AdoptRef(new (&ac) PciMmioConfig(base)); [all...] |
H A D | pcie_bus_driver.cpp | 399 zx_status_t PcieBusDriver::AddSubtractBusRegion(uint64_t base, 411 uint64_t end = base + size - 1; 422 return (mmio_lo.*OpPtr)({ .base = base, .size = size }, true); 424 if (base > U32_MAX) { 425 return (mmio_hi.*OpPtr)({ .base = base, .size = size }, true); 427 uint64_t lo_base = base; 433 res = (mmio_lo.*OpPtr)({ .base = lo_base, .size = lo_size }, true); 437 return (mmio_hi.*OpPtr)({ .base [all...] |
/fuchsia/zircon/kernel/lib/unittest/ |
H A D | user_memory.cpp | 15 zx_status_t status = mapping_->Unmap(mapping_->base(), mapping_->size()); 48 zx_status_t status = mapping->Unmap(mapping->base(), mapping->size());
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/fuchsia/zircon/kernel/vm/include/vm/ |
H A D | arch_vm_aspace.h | 32 // per arch base class api to encapsulate the mmu routines on an aspace 37 virtual zx_status_t Init(vaddr_t base, size_t size, uint mmu_flags) = 0; 61 virtual vaddr_t PickSpot(vaddr_t base, uint prev_region_mmu_flags,
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H A D | vm_object_physical.h | 28 static zx_status_t Create(paddr_t base, uint64_t size, fbl::RefPtr<VmObject>* vmo); 49 VmObjectPhysical(paddr_t base, uint64_t size);
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/fuchsia/zircon/kernel/vm/ |
H A D | vm_address_region_or_mapping.cpp | 23 vaddr_t base, size_t size, uint32_t flags, 25 : state_(LifeCycleState::NOT_READY), base_(base), size_(size), 22 VmAddressRegionOrMapping( vaddr_t base, size_t size, uint32_t flags, VmAspace* aspace, VmAddressRegion* parent) argument
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H A D | vm_object_physical.cpp | 24 VmObjectPhysical::VmObjectPhysical(paddr_t base, uint64_t size) argument 25 : size_(size), base_(base) { 36 zx_status_t VmObjectPhysical::Create(paddr_t base, uint64_t size, fbl::RefPtr<VmObject>* obj) { argument 37 if (!IS_PAGE_ALIGNED(base) || !IS_PAGE_ALIGNED(size) || size == 0) { 41 // check that base + size is a valid range 43 if (add_overflow(base, size - 1, &safe_base)) { 48 auto vmo = fbl::AdoptRef<VmObject>(new (&ac) VmObjectPhysical(base, size)); 68 printf("object %p base %#" PRIxPTR " size %#" PRIx64 " ref %d\n", this, base_, size_, ref_count_debug());
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/fuchsia/zircon/system/dev/block/ahci/ |
H A D | sata.c | 25 #define sata_devinfo_u32(base, offs) (((uint32_t)(base)[(offs) + 1] << 16) | ((uint32_t)(base)[(offs)])) 26 #define sata_devinfo_u64(base, offs) (((uint64_t)(base)[(offs) + 3] << 48) | ((uint64_t)(base)[(offs) + 2] << 32) | ((uint64_t)(base)[(offs) + 1] << 16) | ((uint32_t)(base)[(offs)]))
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/fuchsia/zircon/system/dev/display/intel-i915/ |
H A D | gtt.h | 31 uint64_t base() const { return region_->base; } function in class:i915::GttRegion
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/fuchsia/zircon/system/dev/lib/amlogic/include/soc/aml-common/ |
H A D | aml-gpu.h | 32 #define CALCULATE_CLOCK_MUX(enabled, base, divisor) \ 33 ((!!(enabled) << CLK_ENABLED_BIT_SHIFT) | (base << 9) | (divisor - 1))
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/fuchsia/zircon/system/ulib/launchpad/ |
H A D | elf.c | 67 zx_vaddr_t* base, zx_vaddr_t* entry) { 69 segments_vmar, base, entry); 64 elf_load_finish(zx_handle_t vmar, elf_load_info_t* info, zx_handle_t vmo, zx_handle_t* segments_vmar, zx_vaddr_t* base, zx_vaddr_t* entry) argument
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/fuchsia/zircon/kernel/arch/x86/ |
H A D | mmu_tests.cpp | 20 vaddr_t base = 1UL << 20; local 21 size_t size = (1UL << 47) - base - (1UL << 20); 80 vaddr_t base = 1UL << 20; local 81 size_t size = (1UL << 47) - base - (1UL << 20); 125 vaddr_t base = 1UL << 20; local 126 size_t size = (1UL << 47) - base - (1UL << 20);
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H A D | mmu_mem_types.cpp | 233 static void print_fixed_range_mtrr(uint32_t msr, uint32_t base, uint32_t record_size) { argument 236 printf(" f %#05x-%#05x: %#02x\n", base, base + record_size - 1, (uint8_t)val); 237 base += record_size; 287 uint64_t base = read_msr(IA32_MTRR_PHYSBASE(i)); local 289 printf(" v (%s) base %#016llx, mask %#016llx: %#02x\n", 291 MTRR_PHYSBASE_BASE(base), 293 MTRR_PHYSBASE_TYPE(base));
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/fuchsia/zircon/kernel/object/ |
H A D | vm_address_region_dispatcher.cpp | 204 zx_status_t VmAddressRegionDispatcher::Protect(vaddr_t base, size_t len, uint32_t flags) { argument 207 if (!IS_PAGE_ALIGNED(base)) { 224 return vmar_->Protect(base, len, arch_mmu_flags); 227 zx_status_t VmAddressRegionDispatcher::Unmap(vaddr_t base, size_t len) { argument 230 if (!IS_PAGE_ALIGNED(base)) { 234 return vmar_->Unmap(base, len);
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/fuchsia/zircon/third_party/ulib/musl/src/stdio/ |
H A D | vfscanf.c | 60 int base; local 317 base = 16; 320 base = 8; 324 base = 10; 327 base = 0; 329 x = __intscan(f, base, 0, ULLONG_MAX);
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/fuchsia/zircon/system/dev/bus/acpi/ |
H A D | pci.c | 228 // configuration access method, the base address of the memory mapped 231 arg->addr_windows[0].base = table_start->Address + size_per_bus * arg->addr_windows[0].bus_start; 332 arg->addr_windows[0].base = 0; 408 uint64_t base = 0; local 420 base = mem.minimum; 444 base = addr.minimum; 445 len = addr.maximum - base + 1; 466 base = io.minimum; 478 if (add_range && is_mmio && base < 1024 * 1024) { 486 add_range ? "add" : "subtract", is_mmio ? "MMIO" : "PIO", base, le [all...] |
/fuchsia/zircon/system/ulib/region-alloc/include/region-alloc/ |
H A D | region-alloc.h | 23 // A Region consists of an unsigned 64-bit base address and an unsigned 64-bit 33 // by asking for a specific base/size. The RegionAllocator will manage all of 100 // alloc.AddRegion({ .base = 0xC0000000, . size = 0x40000000 }); // [3GB, 4GB) 101 // alloc.AddRegion({ .base = 0x4000000000, .size = 0x40000000 }); // [256GB, 257GB) 122 // printf("R3 base %llx size %llx\n", r3->base, r3->size) 125 // printf("R8 base %llx size %llx\n", r8->base, r8->size) 151 uint64_t base; member in struct:ralloc_region 173 // ++ GetSpecific (allocates a region based on specific base/siz [all...] |