/linux-master/arch/arm64/boot/dts/freescale/ |
H A D | imx8ulp-pinfunc.h | 13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0 14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1 16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1 23 #define MX8ULP_PAD_PTD1__PTD1 0x0004 0x0000 0x1 0x0 24 #define MX8ULP_PAD_PTD1__I2S6_RX_FS 0x0004 0x0B48 0x7 0x1 26 #define MX8ULP_PAD_PTD1__FLEXSPI2_B_DATA7 0x0004 0x0970 0x9 0x1 32 #define MX8ULP_PAD_PTD2__PTD2 0x0008 0x0000 0x1 0x0 33 #define MX8ULP_PAD_PTD2__I2S6_RXD0 0x0008 0x0B34 0x7 0x1 35 #define MX8ULP_PAD_PTD2__FLEXSPI2_B_DATA6 0x0008 0x096C 0x9 0x1 41 #define MX8ULP_PAD_PTD3__PTD3 0x000C 0x0000 0x1 [all...] |
/linux-master/scripts/dtc/include-prefixes/arm64/freescale/ |
H A D | imx8ulp-pinfunc.h | 13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0 14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1 16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1 23 #define MX8ULP_PAD_PTD1__PTD1 0x0004 0x0000 0x1 0x0 24 #define MX8ULP_PAD_PTD1__I2S6_RX_FS 0x0004 0x0B48 0x7 0x1 26 #define MX8ULP_PAD_PTD1__FLEXSPI2_B_DATA7 0x0004 0x0970 0x9 0x1 32 #define MX8ULP_PAD_PTD2__PTD2 0x0008 0x0000 0x1 0x0 33 #define MX8ULP_PAD_PTD2__I2S6_RXD0 0x0008 0x0B34 0x7 0x1 35 #define MX8ULP_PAD_PTD2__FLEXSPI2_B_DATA6 0x0008 0x096C 0x9 0x1 41 #define MX8ULP_PAD_PTD3__PTD3 0x000C 0x0000 0x1 [all...] |
/linux-master/arch/sh/include/uapi/asm/ |
H A D | cachectl.h | 7 #define CACHEFLUSH_D_INVAL 0x1 /* invalidate (without write back) */
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/linux-master/include/linux/ceph/ |
H A D | ceph_hash.h | 5 #define CEPH_STR_HASH_LINUX 0x1 /* linux dcache hash */
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/linux-master/include/uapi/linux/ |
H A D | if_plip.h | 25 #define PLIP_GET_TIMEOUT 0x1
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/linux-master/fs/afs/ |
H A D | afs_cm.h | 27 #define AFS_CAP_ERROR_TRANSLATION 0x1
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/linux-master/include/linux/platform_data/ |
H A D | ad5449.h | 23 AD5449_SDO_DRIVE_WEAK = 0x1,
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/linux-master/scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/ |
H A D | irq-st.h | 23 #define ST_IRQ_SYSCFG_EXT_1_INV 0x1
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/linux-master/include/dt-bindings/interrupt-controller/ |
H A D | irq-st.h | 23 #define ST_IRQ_SYSCFG_EXT_1_INV 0x1
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/linux-master/scripts/dtc/include-prefixes/dt-bindings/sound/ |
H A D | adi,adau1977.h | 6 #define ADAU1977_MICBIAS_5V5 0x1
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/linux-master/include/dt-bindings/sound/ |
H A D | adi,adau1977.h | 6 #define ADAU1977_MICBIAS_5V5 0x1
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/linux-master/arch/arm/mach-bcm/ |
H A D | bcm_kona_smc.h | 12 #define SEC_EXIT_NORMAL 0x1
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/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
H A D | polaris_baco.c | 53 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x1, 0x0, 0, 0x1 }, 59 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT, 0, 0x1 }, 61 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x4000000, 0x1a, 0, 0x1 }, 63 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK, GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT, 0, 0x1 }, 66 { CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL_MASK, MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL__SHIFT, 0, 0x1 }, 71 { CMD_READMODIFYWRITE, mmDC_GPIO_PAD_STRENGTH_1, DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK, DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT, 0, 0x1 }, 73 { CMD_READMODIFYWRITE, mmMC_SEQ_DRAM, MC_SEQ_DRAM__RST_CTL_MASK, MC_SEQ_DRAM__RST_CTL__SHIFT, 0, 0x1 }, 75 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x10, 0x4, 0, 0x1 }, 78 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x10, 0x4, 0, 0x1 }, [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
H A D | dalsmc.h | 29 #define DALSMC_VERSION 0x1 32 #define DALSMC_Result_OK 0x1 39 #define DALSMC_MSG_TestMessage 0x1 62 #define CHECK_HARD_MIN_CLK_DISPCLK 0x1
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/linux-master/arch/arm64/kvm/hyp/ |
H A D | fpsimd.S | 25 sve_load 0, x1, x2, 3 31 sve_save 0, x1, x2, 3
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/linux-master/sound/soc/codecs/ |
H A D | tas2552.h | 44 #define TAS2552_PLL_SRC_BCLK (0x1 << 4) 59 #define TAS2552_WCLK_FREQ_11_12KHZ (0x1 << 0) 68 #define TAS2552_DIN_SRC_SEL_LEFT (0x1 << 3) 80 #define TAS2552_WORDLENGTH_20BIT (0x1 << 0) 85 #define TAS2552_DATAFORMAT_DSP (0x1 << 2) 90 #define TAS2552_CLKSPERFRAME_64 (0x1 << 4) 99 #define TAS2552_DATA_OUT_V_DATA (0x1) 109 #define TAS2552_PDM_DATA_SEL_V (0x1 << 6) 116 #define TAS2552_PDM_CLK_SEL_IVCLKIN (0x1 << 0) 124 #define TAS2552_APT_DELAY_75 (0x1 << [all...] |
/linux-master/arch/arm64/kernel/ |
H A D | hyp-stub.S | 51 msr vbar_el2, x1 61 mov x4, x1 62 mov x1, x3 81 mrs x1, sctlr_el2 82 tbnz x1, #0, 1f 85 check_override id_aa64mmfr1 ID_AA64MMFR1_EL1_VH_SHIFT 0f 1f x1 x2 88 adr_l x1, arm64_sw_feature_override 89 ldr x2, [x1, FTR_OVR_VAL_OFFSET] 90 ldr x1, [x1, FTR_OVR_MASK_OFFSE [all...] |
/linux-master/include/uapi/drm/ |
H A D | vgem_drm.h | 39 #define DRM_VGEM_FENCE_ATTACH 0x1 48 #define VGEM_FENCE_WRITE 0x1
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/linux-master/include/uapi/linux/netfilter/ |
H A D | xt_statistic.h | 15 XT_STATISTIC_INVERT = 0x1, 17 #define XT_STATISTIC_MASK 0x1
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/linux-master/drivers/nfc/st95hf/ |
H A D | spi.h | 16 #define ST95HF_COMMAND_RESET 0x1 19 #define ST95HF_RESET_CMD_LEN 0x1
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/linux-master/arch/x86/crypto/ |
H A D | glue_helper-asm-avx2.S | 8 #define load_16way(src, x0, x1, x2, x3, x4, x5, x6, x7) \ 10 vmovdqu (1*32)(src), x1; \ 18 #define store_16way(dst, x0, x1, x2, x3, x4, x5, x6, x7) \ 20 vmovdqu x1, (1*32)(dst); \ 28 #define store_cbc_16way(src, dst, x0, x1, x2, x3, x4, x5, x6, x7, t0) \ 32 vpxor (0*32+16)(src), x1, x1; \ 39 store_16way(dst, x0, x1, x2, x3, x4, x5, x6, x7);
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/linux-master/drivers/soc/mediatek/ |
H A D | mt8167-mmsys.h | 12 #define MT8167_DITHER_MOUT_EN_RDMA0 0x1 14 #define MT8167_DSI0_SEL_IN_RDMA0 0x1
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/linux-master/arch/mips/include/asm/octeon/ |
H A D | cvmx-helper-board.h | 47 set_phy_link_flags_autoneg = 0x1, 49 set_phy_link_flags_flow_control_enable = 0x1 << 1,
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/linux-master/arch/arm64/kvm/hyp/nvhe/ |
H A D | cache.S | 11 dcache_by_line_op civac, sy, x0, x1, x2, x3 22 invalidate_icache_by_line x0, x1, x2, x3
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/linux-master/drivers/net/ethernet/mellanox/mlx5/core/sf/ |
H A D | mlx5_ifc_vhca_event.h | 9 MLX5_VHCA_STATE_ALLOCATED = 0x1, 16 u8 arm_change_event[0x1]; 44 u8 embedded_cpu_function[0x1]; 53 u8 sw_function_id[0x1]; 54 u8 arm_change_event[0x1]; 73 u8 embedded_cpu_function[0x1];
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