Searched refs:getRegClassFor (Results 26 - 38 of 38) sorted by relevance
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| /freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGISel.cpp | 1279 TLI->getRegClassFor(TLI->getPointerTy(CurDAG->getDataLayout()));
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| H A D | SelectionDAGBuilder.cpp | 7329 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
9521 : RegVT != MVT::Untyped ? TLI.getRegClassFor(RegVT)
11140 RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
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| H A D | DAGCombiner.cpp | 19113 TLI.getRegClassFor(ResVT.getSimpleVT(), Use->isDivergent());
19115 TLI.getRegClassFor(Use->getOperand(0).getValueType().getSimpleVT(),
[all...] |
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 1380 MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrVT));
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 471 MF.addLiveIn(VA.getLocReg(), getRegClassFor(VA.getLocVT()));
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| /freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineScheduler.cpp | 3255 TLI->getRegClassFor(LegalIntVT));
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| /freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 980 virtual const TargetRegisterClass *getRegClassFor(MVT VT, bool isDivergent = false) const { function
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 6245 Register Reg = MF.addLiveIn(TRI->getReturnAddressReg(MF), getRegClassFor(VT, Op.getNode()->isDivergent()));
14760 getRegClassFor(VT, Src0.getNode()->isDivergent());
15899 SITargetLowering::getRegClassFor(MVT VT, bool isDivergent) const {
15900 const TargetRegisterClass *RC = TargetLoweringBase::getRegClassFor(VT, false);
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 1917 /// getRegClassFor - Return the register class that should be used for the
1920 ARMTargetLowering::getRegClassFor(MVT VT, bool isDivergent) const { function in class:ARMTargetLowering
1938 return TargetLowering::getRegClassFor(VT);
4088 Register Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
6122 Register Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 722 if (UseX87 && (getRegClassFor(MVT::f32) == &X86::RFP32RegClass)) {
732 if (UseX87 && getRegClassFor(MVT::f64) == &X86::RFP64RegClass) {
24751 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
24780 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 7423 Register Reg = MF.addLiveIn(RI.getRARegister(), getRegClassFor(XLenVT));
17406 const TargetRegisterClass *RC = TLI.getRegClassFor(ValVT);
17776 const TargetRegisterClass *RC = TLI.getRegClassFor(LocVT.getSimpleVT());
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 6927 getRegClassFor(PStateSM.getValueType().getSimpleVT()));
6940 getRegClassFor(InVals[I].getValueType().getSimpleVT()));
6996 MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
8214 getRegClassFor(InVals[I].getValueType().getSimpleVT()));
[all...] |
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 12297 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
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