Searched refs:OS_REG_READ (Results 51 - 75 of 104) sorted by relevance

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/freebsd-current/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_reset.c135 regval = OS_REG_READ(ah, AR_USEC);
328 nf = (OS_REG_READ(ah, regs[i]) & masks[chan]) >> shifts[chan];
351 if ((OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0) {
352 nf = MS(OS_REG_READ(ah, AR_PHY_CCA_0), AR9280_PHY_MINCCA_PWR);
633 if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
875 OS_REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO;
898 phymode |= OS_REG_READ(ah, AR_PHY_GEN_CTRL);
907 u_int32_t modeselect = OS_REG_READ(ah, AR_PHY_MODE);
1220 OS_REG_READ(ah, AR_PHY_TIMING4));
1222 OS_REG_READ(a
[all...]
H A Dar9300_mci.c127 data = OS_REG_READ(ah, address);
159 OS_REG_READ(ah, AR_MCI_INTERRUPT_RAW),
160 OS_REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW));
542 (OS_REG_READ(ah, AR_GLB_GPIO_CONTROL) |
768 saved_mci_int_en = OS_REG_READ(ah, AR_MCI_INTERRUPT_EN);
772 OS_REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW));
774 OS_REG_READ(ah, AR_MCI_INTERRUPT_RAW));
1011 if (OS_REG_READ(ah, AR_BTCOEX_CTRL) == 0xdeadbeef) {
1138 regval = OS_REG_READ(ah, AR_MCI_COMMAND2);
1290 u_int32_t saved_mci_int_en = OS_REG_READ(a
[all...]
H A Dar9300_xmit_ds.c466 OS_REG_READ(ah, AR_Q_TXE),
467 OS_REG_READ(ah, AR_Q_TXD)
470 val = OS_REG_READ(ah, AR_QTXDP(i));
471 val2 = OS_REG_READ(ah, AR_QSTS(i)) & AR_Q_STS_PEND_FR_CNT;
490 (OS_REG_READ(ah, AR_PHY_TEST) | PHY_AGC_CLR) );
492 OS_REG_WRITE(ah, 0x9864, OS_REG_READ(ah, 0x9864) | 0x7f000);
493 OS_REG_WRITE(ah, 0x9924, OS_REG_READ(ah, 0x9924) | 0x7f00fe);
495 (OS_REG_READ(ah, AR_DIAG_SW) |
560 (OS_REG_READ(ah, AR_PHY_TEST) & ~PHY_AGC_CLR));
562 (OS_REG_READ(a
[all...]
H A Dar9300_aic.c302 value = OS_REG_READ(ah, AR_PHY_AIC_SRAM_DATA_B1);
583 (OS_REG_READ(ah, ATH_AIC_BT_JUPITER_CTRL) |
602 if ((OS_REG_READ(ah, aic_ctrl_b1[0]) & AR_PHY_AIC_CAL_ENABLE) == 0)
611 aic_stat = OS_REG_READ(ah, aic_stat_b1[0]);
627 aic_stat = OS_REG_READ(ah, aic_stat_b1[1]);
644 value = OS_REG_READ(ah, AR_PHY_AIC_SRAM_DATA_B1);
661 (OS_REG_READ(ah, ATH_AIC_BT_JUPITER_CTRL) &
H A Dar9300_paprd.c58 u_int32_t val = OS_REG_READ(ah, AR_2040_MODE);
445 u_int32_t val = OS_REG_READ(ah, AR_2040_MODE);
662 gain_table_entries[i] = OS_REG_READ(ah, reg);
1294 paprd_train_data_l[i] = OS_REG_READ(ah, reg);
1309 paprd_train_data_u[i] = OS_REG_READ(ah, reg);
1847 (unsigned) AR_PHY_PA_GAIN123_B0, OS_REG_READ(ah, AR_PHY_PA_GAIN123_B0));
1852 (unsigned) AR_PHY_PAPRD_CTRL1_B0, OS_REG_READ(ah, AR_PHY_PAPRD_CTRL1_B0));
1900 if (OS_REG_READ(ah, reg) == 0xdeadbeef) {
1906 if (OS_REG_READ(ah, j) == 0xdeadbeef) {
1914 if (OS_REG_READ(a
[all...]
H A Dar9300_ani.c312 val = OS_REG_READ(ah, AR_PHY_SFCORR);
317 val = OS_REG_READ(ah, AR_PHY_SFCORR_LOW);
325 val = OS_REG_READ(ah, AR_PHY_SFCORR_EXT);
1029 if (!(OS_REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING)) {
1048 phy_cnt1 = OS_REG_READ(ah, AR_PHY_ERR_1);
1049 phy_cnt2 = OS_REG_READ(ah, AR_PHY_ERR_2);
1112 tx_frame_count = OS_REG_READ(ah, AR_TFCNT);
1113 rx_frame_count = OS_REG_READ(ah, AR_RFCNT);
1114 rx_busy_count = OS_REG_READ(ah, AR_RCCNT);
1115 rx_ext_busy_count = OS_REG_READ(a
[all...]
/freebsd-current/sys/dev/ath/ath_hal/ar5211/
H A Dar5211_xmit.c48 txcfg = OS_REG_READ(ah, AR_TXCFG);
293 OS_REG_READ(ah, AR_QMISC(q)) |
309 OS_REG_READ(ah, AR_QMISC(q)) |
316 OS_REG_READ(ah, AR_DMISC(q)) |
321 OS_REG_READ(ah, AR_DMISC(q)) |
328 OS_REG_READ(ah, AR_QMISC(q))
342 OS_REG_READ(ah, AR_QMISC(q))
405 return OS_REG_READ(ah, AR_QTXDP(q));
421 HALASSERT((OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) == 0);
438 HALASSERT((OS_REG_READ(a
[all...]
H A Dar5211_attach.c198 val = (OS_REG_READ(ah, AR_PHY_BASE + (256 << 2)) >> 24) & 0xff;
264 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID_M;
277 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
304 val = (OS_REG_READ(ah, AR_PCICFG) & AR_PCICFG_EEPROM_SIZE_M) >>
403 regHold[i] = OS_REG_READ(ah, addr);
407 rdData = OS_REG_READ(ah, addr);
418 rdData = OS_REG_READ(ah, addr);
/freebsd-current/sys/dev/ath/ath_hal/ar5212/
H A Dar5212_beacon.c35 return TU_TO_TSF(OS_REG_READ(ah, AR_TIMER0));
132 val = OS_REG_READ(ah, AR_STA_ID1);
156 OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PCF);
169 OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_PCF);
185 (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM))
H A Dar5212_xmit.c60 txcfg = OS_REG_READ(ah, AR_TXCFG);
470 OS_REG_READ(ah, AR_Q0_MISC + 4*q)
517 return OS_REG_READ(ah, AR_QTXDP(q));
533 HALASSERT((OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) == 0);
553 HALASSERT((OS_REG_READ(ah, AR_Q_TXD) & (1 << q)) == 0);
571 npend = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
578 if (OS_REG_READ(ah, AR_Q_TXE) & (1 << q))
609 OS_REG_READ(ah, AR_QSTS(q)), OS_REG_READ(ah, AR_Q_TXE),
610 OS_REG_READ(a
[all...]
H A Dar5212_reset.c197 saveFrameSeqCount = OS_REG_READ(ah, AR_D_SEQNUM);
237 saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA);
242 macStaId1 = OS_REG_READ(ah, AR_STA_ID1) &
246 saveLedState = OS_REG_READ(ah, AR_PCICFG) &
249 softLedCfg = OS_REG_READ(ah, AR_GPIOCR);
250 softLedState = OS_REG_READ(ah, AR_GPIODO);
386 if (OS_REG_READ(ah, AR_PHY_FAST_ADC) != newReg)
438 OS_REG_WRITE(ah, AR_PCICFG, OS_REG_READ(ah, AR_PCICFG) | saveLedState);
498 synthDelay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
527 testReg = OS_REG_READ(a
[all...]
H A Dar5212_ani.c690 __func__, OS_REG_READ(ah, AR_MIBC),
691 OS_REG_READ(ah, AR_PHYCNT1), OS_REG_READ(ah, AR_PHYCNT2),
692 OS_REG_READ(ah, AR_FILTOFDM), OS_REG_READ(ah, AR_FILTCCK));
704 phyCnt1 = OS_REG_READ(ah, AR_PHYCNT1);
705 phyCnt2 = OS_REG_READ(ah, AR_PHYCNT2);
943 phyCnt1 = OS_REG_READ(ah, AR_PHYCNT1);
944 phyCnt2 = OS_REG_READ(ah, AR_PHYCNT2);
/freebsd-current/sys/dev/ath/ath_hal/ar5312/
H A Dar5312_attach.c139 val = ((OS_REG_READ(ah, (AR5315_RSTIMER_BASE -((uint32_t) sh)) + AR5315_WREV)) >> AR5315_WREV_S)
149 val = OS_REG_READ(ah, (AR5312_RSTIMER_BASE - ((uint32_t) sh)) + 0x0020);
150 val = OS_REG_READ(ah, (AR5312_RSTIMER_BASE - ((uint32_t) sh)) + 0x0080);
152 val = ((OS_REG_READ(ah, (AR5312_RSTIMER_BASE - ((uint32_t) sh)) + AR5312_WREV)) >> AR5312_WREV_S) & AR5312_WREV_ID;
171 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
H A Dar5312_misc.c47 (OS_REG_READ(ah, AR5312_PCICFG) &~
70 v = (OS_REG_READ(ah,
81 v = (OS_REG_READ(ah,
/freebsd-current/sys/dev/ath/ath_hal/ar9002/
H A Dar9287.c85 reg32 = OS_REG_READ(ah, AR_PHY_SYNTH_CONTROL);
109 txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);
299 nf = MS(OS_REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
306 nf = MS(OS_REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR);
313 nf = MS(OS_REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);
320 nf = MS(OS_REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR);
H A Dar9280.c86 reg32 = OS_REG_READ(ah, AR_PHY_SYNTH_CONTROL);
100 txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);
357 nf = MS(OS_REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
364 nf = MS(OS_REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR);
371 nf = MS(OS_REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);
378 nf = MS(OS_REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR);
H A Dar9285_btcoex.c105 regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
120 regVal = OS_REG_READ(ah, AR_PHY_CCK_DETECT);
H A Dar9280_olc.c53 AH9280(ah)->originalGain[i] = MS(OS_REG_READ(ah,
138 rddata = OS_REG_READ(ah, AR_PHY_TX_PWRCTRL4);
305 pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
/freebsd-current/sys/dev/ath/ath_hal/ar5210/
H A Dar5210_xmit.c190 (OS_REG_READ(ah, AR_PHY(17)) & ~0x7F) | 0x38);
207 (OS_REG_READ(ah, AR_PHY(17)) & ~0x7F) | 0x1C);
267 return OS_REG_READ(ah, AR_TXDP0);
300 if (OS_REG_READ(ah, AR_CR) & AR_CR_TXE0)
302 __func__, OS_REG_READ(ah, AR_CR));
339 curTrigLevel = OS_REG_READ(ah, AR_TRIG_LEV);
412 v = OS_REG_READ(ah, AR_CFG);
442 if ((OS_REG_READ(ah, AR_CFG) & AR_CFG_TXCNT) == 0)
H A Dar5210_attach.c242 AH_PRIVATE(ah)->ah_macRev = OS_REG_READ(ah, AR_SREV) & 0xff;
243 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIPID);
250 revid = (OS_REG_READ(ah, AR_PHY_BASE + (256 << 2)) >> 28) & 0xf;
259 pcicfg = OS_REG_READ(ah, AR_PCICFG);
/freebsd-current/sys/dev/ath/
H A Dah_osdep.h138 #define OS_REG_READ(_ah, _reg) ath_hal_reg_read(_ah, _reg) macro
/freebsd-current/sys/dev/ath/ath_hal/ar5416/
H A Dar5416_reset.c133 rssiThrReg = OS_REG_READ(ah, AR_RSSI_THR);
141 saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA);
159 macStaId1 = OS_REG_READ(ah, AR_STA_ID1) &
163 saveLedState = OS_REG_READ(ah, AR_MAC_LED) &
225 __func__, OS_REG_READ(ah,AR_PHY_DAG_CTRLCCK));
227 __func__, OS_REG_READ(ah,AR_PHY_ADC_CTL));
288 OS_REG_WRITE(ah, AR_MAC_LED, OS_REG_READ(ah, AR_MAC_LED) |
391 OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
463 reg = (OS_REG_READ(ah, AR_STA_ID1) | (1<<22));
540 data = OS_REG_READ(a
[all...]
H A Dar2133.c157 txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);
451 nf = MS(OS_REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR);
458 nf = MS(OS_REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR);
467 nf = MS(OS_REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR);
474 nf = MS(OS_REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);
482 nf = MS(OS_REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
489 nf = MS(OS_REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
H A Dar5416_ani.c658 __func__, OS_REG_READ(ah, AR_MIBC),
659 OS_REG_READ(ah, AR_PHYCNT1), OS_REG_READ(ah, AR_PHYCNT2),
660 OS_REG_READ(ah, AR_FILTOFDM), OS_REG_READ(ah, AR_FILTCCK));
672 phyCnt1 = OS_REG_READ(ah, AR_PHY_ERR_1);
673 phyCnt2 = OS_REG_READ(ah, AR_PHY_ERR_2);
677 if ((OS_REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING) == 0)
889 phyCnt1 = OS_REG_READ(ah, AR_PHY_ERR_1);
890 phyCnt2 = OS_REG_READ(a
[all...]
/freebsd-current/sys/dev/ath/ath_hal/ar9001/
H A Dar9160_attach.c167 val = OS_REG_READ(ah, AR_SREV);
207 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
278 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);

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