Searched refs:MCInstrDesc (Results 51 - 75 of 206) sorted by relevance

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/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp95 #include "llvm/MC/MCInstrDesc.h"
692 const MCInstrDesc &MCID = Builder.getInstr()->getDesc();
1219 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
1979 Register FastISel::constrainOperandRegClass(const MCInstrDesc &II, Register Op,
1999 const MCInstrDesc &II = TII.get(MachineInstOpcode);
2007 const MCInstrDesc &II = TII.get(MachineInstOpcode);
2029 const MCInstrDesc &II = TII.get(MachineInstOpcode);
2053 const MCInstrDesc &II = TII.get(MachineInstOpcode);
2080 const MCInstrDesc &II = TII.get(MachineInstOpcode);
2103 const MCInstrDesc
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H A DScheduleDAGSDNodes.cpp130 const MCInstrDesc &II = TII->get(Def->getMachineOpcode());
215 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
321 const MCInstrDesc &MCID = TII->get(Opc);
453 const MCInstrDesc &MCID = TII->get(Opc);
/freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DScheduleDAG.h38 class MCInstrDesc;
587 /// Returns the MCInstrDesc of this SUnit.
589 const MCInstrDesc *getInstrDesc(const SUnit *SU) const {
621 /// Returns the MCInstrDesc of this SDNode or NULL.
622 const MCInstrDesc *getNodeDesc(const SDNode *Node) const;
H A DFastISel.h52 class MCInstrDesc;
466 /// provided MCInstrDesc. If this fails, create a new virtual register in the
468 Register constrainOperandRegClass(const MCInstrDesc &II, Register Op,
H A DMachineFunction.h65 class MCInstrDesc;
466 /// Callback before changing MCInstrDesc. This should not modify the MI
468 virtual void MF_HandleChangeDesc(MachineInstr &MI, const MCInstrDesc &TID) {
507 void handleChangeDesc(MachineInstr &MI, const MCInstrDesc &TID);
990 MachineInstr *CreateMachineInstr(const MCInstrDesc &MCID, DebugLoc DL,
/freebsd-current/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrInfo.cpp412 const MCInstrDesc &MID = MI.getDesc();
418 const MCInstrDesc &MID = MI.getDesc();
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.h30 class MCInstrDesc;
126 MCInstrDesc const &getDesc(MCInstrInfo const &MCII, MCInst const &MCI);
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.h18 class MCInstrDesc;
163 bool needsImpliedVcc(const MCInstrDesc &Desc, unsigned OpNo) const;
/freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h42 class MCInstrDesc;
117 /// MCInstrDesc \p II. If this fails, create a new virtual register in the
122 /// with RegClass obtained from the MCInstrDesc. The debug location of \p
131 MachineInstr &InsertPt, const MCInstrDesc &II,
/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrBuilder.h33 #include "llvm/MC/MCInstrDesc.h"
202 const MCInstrDesc &MCID = MI->getDesc();
H A DX86InsertPrefetch.cpp220 const MCInstrDesc &Desc = TII->get(PFetchInstrID);
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiDelaySlotFiller.cpp227 const MCInstrDesc &MCID = MI->getDesc();
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64DeadRegisterDefinitionsPass.cpp141 const MCInstrDesc &Desc = MI.getDesc();
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/
H A DBreakFalseDeps.cpp27 #include "llvm/MC/MCInstrDesc.h"
192 const MCInstrDesc &MCID = MI->getDesc();
H A DSplitKit.h441 const MCInstrDesc &Desc);
/freebsd-current/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.cpp41 #include "llvm/MC/MCInstrDesc.h"
532 const MCInstrDesc &Desc = MI->getDesc();
680 const MCInstrDesc &MCID = TII.get(ADDriOpc);
724 const MCInstrDesc &Desc = MI->getDesc();
854 const MCInstrDesc &MCID = MI.getDesc();
H A DThumb2ITBlockPass.cpp26 #include "llvm/MC/MCInstrDesc.h"
170 const MCInstrDesc &MCID = MI->getDesc();
/freebsd-current/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrInfo.cpp439 const MCInstrDesc &Desc, MVT MVTDst,
476 const MCInstrDesc &Desc, bool IsPush) const {
509 const MCInstrDesc &Desc, bool IsRM) const {
563 const MCInstrDesc &Desc) {
/freebsd-current/contrib/llvm-project/llvm/lib/Target/MSP430/MCTargetDesc/
H A DMSP430MCCodeEmitter.cpp86 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRMCCodeEmitter.cpp277 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
/freebsd-current/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyMCCodeEmitter.cpp92 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
/freebsd-current/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInstrDesc.h1 //===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
9 // This file defines the MCOperandInfo and MCInstrDesc classes, which
145 /// MCInstrDesc class. Clients should use the predicate methods on MCInstrDesc,
147 /// MCInstrDesc::Flags field.
198 class MCInstrDesc { class in namespace:llvm
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.cpp604 ComponentProps::ComponentProps(const MCInstrDesc &OpDesc) {
689 VOPD::InstInfo getVOPDInstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY) {
2378 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) {
2385 bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo) {
2392 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo) {
2418 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo) {
2572 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
2925 bool hasAny64BitVGPROperands(const MCInstrDesc &OpDesc) {
2940 bool isDPALU_DPP(const MCInstrDesc
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86AsmBackend.cpp242 const MCInstrDesc &Desc = MCII.get(Opcode);
258 const MCInstrDesc &Desc = MCII.get(Opcode);
297 const MCInstrDesc &Desc = MCII->get(Inst.getOpcode());
350 const MCInstrDesc &InstDesc = MCII->get(Jcc.getOpcode());
503 const MCInstrDesc &Desc = MCII->get(Inst.getOpcode());
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFrameLowering.cpp183 const MCInstrDesc &SMovB32 = TII->get(AMDGPU::S_MOV_B32);
192 const MCInstrDesc &GetPC64 = TII->get(AMDGPU::S_GETPC_B64_pseudo);
434 const MCInstrDesc &LoadDwordX2 = TII->get(AMDGPU::S_LOAD_DWORDX2_IMM);
451 const MCInstrDesc &SAndB32 = TII->get(AMDGPU::S_AND_B32);
745 const MCInstrDesc &LoadDwordX4 = TII->get(AMDGPU::S_LOAD_DWORDX4_IMM);
769 const MCInstrDesc &SBitsetB32 = TII->get(AMDGPU::S_BITSET0_B32);
776 const MCInstrDesc &SMovB32 = TII->get(AMDGPU::S_MOV_B32);
788 const MCInstrDesc &Mov64 = TII->get(AMDGPU::S_MOV_B64);
794 const MCInstrDesc &LoadDwordX2 = TII->get(AMDGPU::S_LOAD_DWORDX2_IMM);

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