/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FastISel.cpp | 95 #include "llvm/MC/MCInstrDesc.h" 692 const MCInstrDesc &MCID = Builder.getInstr()->getDesc(); 1219 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE); 1979 Register FastISel::constrainOperandRegClass(const MCInstrDesc &II, Register Op, 1999 const MCInstrDesc &II = TII.get(MachineInstOpcode); 2007 const MCInstrDesc &II = TII.get(MachineInstOpcode); 2029 const MCInstrDesc &II = TII.get(MachineInstOpcode); 2053 const MCInstrDesc &II = TII.get(MachineInstOpcode); 2080 const MCInstrDesc &II = TII.get(MachineInstOpcode); 2103 const MCInstrDesc [all...] |
H A D | ScheduleDAGSDNodes.cpp | 130 const MCInstrDesc &II = TII->get(Def->getMachineOpcode()); 215 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); 321 const MCInstrDesc &MCID = TII->get(Opc); 453 const MCInstrDesc &MCID = TII->get(Opc);
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/freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ScheduleDAG.h | 38 class MCInstrDesc; 587 /// Returns the MCInstrDesc of this SUnit. 589 const MCInstrDesc *getInstrDesc(const SUnit *SU) const { 621 /// Returns the MCInstrDesc of this SDNode or NULL. 622 const MCInstrDesc *getNodeDesc(const SDNode *Node) const;
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H A D | FastISel.h | 52 class MCInstrDesc; 466 /// provided MCInstrDesc. If this fails, create a new virtual register in the 468 Register constrainOperandRegClass(const MCInstrDesc &II, Register Op,
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H A D | MachineFunction.h | 65 class MCInstrDesc; 466 /// Callback before changing MCInstrDesc. This should not modify the MI 468 virtual void MF_HandleChangeDesc(MachineInstr &MI, const MCInstrDesc &TID) { 507 void handleChangeDesc(MachineInstr &MI, const MCInstrDesc &TID); 990 MachineInstr *CreateMachineInstr(const MCInstrDesc &MCID, DebugLoc DL,
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCInstrInfo.cpp | 412 const MCInstrDesc &MID = MI.getDesc(); 418 const MCInstrDesc &MID = MI.getDesc();
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCInstrInfo.h | 30 class MCInstrDesc; 126 MCInstrDesc const &getDesc(MCInstrInfo const &MCII, MCInst const &MCI);
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
H A D | AMDGPUInstPrinter.h | 18 class MCInstrDesc; 163 bool needsImpliedVcc(const MCInstrDesc &Desc, unsigned OpNo) const;
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/freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | Utils.h | 42 class MCInstrDesc; 117 /// MCInstrDesc \p II. If this fails, create a new virtual register in the 122 /// with RegClass obtained from the MCInstrDesc. The debug location of \p 131 MachineInstr &InsertPt, const MCInstrDesc &II,
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InstrBuilder.h | 33 #include "llvm/MC/MCInstrDesc.h" 202 const MCInstrDesc &MCID = MI->getDesc();
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H A D | X86InsertPrefetch.cpp | 220 const MCInstrDesc &Desc = TII->get(PFetchInstrID);
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiDelaySlotFiller.cpp | 227 const MCInstrDesc &MCID = MI->getDesc();
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64DeadRegisterDefinitionsPass.cpp | 141 const MCInstrDesc &Desc = MI.getDesc();
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/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | BreakFalseDeps.cpp | 27 #include "llvm/MC/MCInstrDesc.h" 192 const MCInstrDesc &MCID = MI->getDesc();
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H A D | SplitKit.h | 441 const MCInstrDesc &Desc);
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMBaseRegisterInfo.cpp | 41 #include "llvm/MC/MCInstrDesc.h" 532 const MCInstrDesc &Desc = MI->getDesc(); 680 const MCInstrDesc &MCID = TII.get(ADDriOpc); 724 const MCInstrDesc &Desc = MI->getDesc(); 854 const MCInstrDesc &MCID = MI.getDesc();
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H A D | Thumb2ITBlockPass.cpp | 26 #include "llvm/MC/MCInstrDesc.h" 170 const MCInstrDesc &MCID = MI->getDesc();
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/M68k/ |
H A D | M68kInstrInfo.cpp | 439 const MCInstrDesc &Desc, MVT MVTDst, 476 const MCInstrDesc &Desc, bool IsPush) const { 509 const MCInstrDesc &Desc, bool IsRM) const { 563 const MCInstrDesc &Desc) {
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/MSP430/MCTargetDesc/ |
H A D | MSP430MCCodeEmitter.cpp | 86 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/ |
H A D | AVRMCCodeEmitter.cpp | 277 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/ |
H A D | WebAssemblyMCCodeEmitter.cpp | 92 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
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/freebsd-current/contrib/llvm-project/llvm/include/llvm/MC/ |
H A D | MCInstrDesc.h | 1 //===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===// 9 // This file defines the MCOperandInfo and MCInstrDesc classes, which 145 /// MCInstrDesc class. Clients should use the predicate methods on MCInstrDesc, 147 /// MCInstrDesc::Flags field. 198 class MCInstrDesc { class in namespace:llvm
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
H A D | AMDGPUBaseInfo.cpp | 604 ComponentProps::ComponentProps(const MCInstrDesc &OpDesc) { 689 VOPD::InstInfo getVOPDInstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY) { 2378 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) { 2385 bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo) { 2392 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo) { 2418 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo) { 2572 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, 2925 bool hasAny64BitVGPROperands(const MCInstrDesc &OpDesc) { 2940 bool isDPALU_DPP(const MCInstrDesc [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86AsmBackend.cpp | 242 const MCInstrDesc &Desc = MCII.get(Opcode); 258 const MCInstrDesc &Desc = MCII.get(Opcode); 297 const MCInstrDesc &Desc = MCII->get(Inst.getOpcode()); 350 const MCInstrDesc &InstDesc = MCII->get(Jcc.getOpcode()); 503 const MCInstrDesc &Desc = MCII->get(Inst.getOpcode());
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIFrameLowering.cpp | 183 const MCInstrDesc &SMovB32 = TII->get(AMDGPU::S_MOV_B32); 192 const MCInstrDesc &GetPC64 = TII->get(AMDGPU::S_GETPC_B64_pseudo); 434 const MCInstrDesc &LoadDwordX2 = TII->get(AMDGPU::S_LOAD_DWORDX2_IMM); 451 const MCInstrDesc &SAndB32 = TII->get(AMDGPU::S_AND_B32); 745 const MCInstrDesc &LoadDwordX4 = TII->get(AMDGPU::S_LOAD_DWORDX4_IMM); 769 const MCInstrDesc &SBitsetB32 = TII->get(AMDGPU::S_BITSET0_B32); 776 const MCInstrDesc &SMovB32 = TII->get(AMDGPU::S_MOV_B32); 788 const MCInstrDesc &Mov64 = TII->get(AMDGPU::S_MOV_B64); 794 const MCInstrDesc &LoadDwordX2 = TII->get(AMDGPU::S_LOAD_DWORDX2_IMM);
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