Searched refs:CreateReg (Results 26 - 50 of 75) sorted by relevance

123

/freebsd-current/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp474 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind, function in class:__anon2634::SparcOperand
1178 Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E));
1273 Op = SparcOperand::CreateReg(Reg, RegKind, S, E);
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveDebugVariables.cpp865 MachineOperand MO = MachineOperand::CreateReg(0U, false);
1367 MachineOperand MO = MachineOperand::CreateReg(LI->reg(), false);
1678 MachineOperand::CreateReg(
/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86OptimizeLEAs.cpp610 return MachineOperand::CreateReg(NewReg, false, false, false, false,
H A DX86InstrInfo.cpp1447 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1485 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1511 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1549 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
1555 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1605 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1645 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
5741 UseMI.addOperand(MachineOperand::CreateReg(X86::EFLAGS, /*isDef=*/true,
8147 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
8149 MOs.push_back(MachineOperand::CreateReg(
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H A DX86FloatingPoint.cpp1166 MachineOperand::CreateReg(X86::ST0, /*isDef*/ true, /*isImp*/ true));
1214 MachineOperand::CreateReg(X86::ST0, /*isDef*/ false, /*isImp*/ true));
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp430 CreateReg(MCContext &Context, unsigned RegNum, SMLoc S, SMLoc E) { function in struct:__anon2428::HexagonOperand
890 HexagonOperand::CreateReg(getContext(), Register, Begin, End));
908 HexagonOperand::CreateReg(getContext(), Register, Begin, End));
920 HexagonOperand::CreateReg(getContext(), Register, Begin, End));
/freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineOperand.h837 static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp = false,
H A DMachineInstrBuilder.h102 MI->addOperand(*MF, MachineOperand::CreateReg(RegNo,
/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp2542 Operands.push_back(X86Operand::CreateReg(RegNo, Start, End));
2738 Operands.push_back(X86Operand::CreateReg(Reg, Loc, EndLoc));
2863 X86Operand::CreateReg(RegNo, StartLoc, StartLoc));
3546 Operands[1] = X86Operand::CreateReg(Reg, Loc, Loc);
3558 Operands.back() = X86Operand::CreateReg(X86::DX, Op.getStartLoc(),
3567 Operands[1] = X86Operand::CreateReg(X86::DX, Op.getStartLoc(),
3581 X86Operand::CreateReg(X86::DX, NameLoc, NameLoc),
3592 X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
H A DX86Operand.h676 CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc, function in struct:llvm::final
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp2234 CreateReg(unsigned RegNum, RegKind Kind, SMLoc S, SMLoc E, MCContext &Ctx, function in class:__anon2225::AArch64Operand
2262 auto Op = CreateReg(RegNum, Kind, S, E, Ctx, EqualsReg, ExtTy, ShiftAmount,
3169 Operands.push_back(AArch64Operand::CreateReg(
4575 Operands.push_back(AArch64Operand::CreateReg(
4590 Operands.push_back(AArch64Operand::CreateReg(
4605 Operands.push_back(AArch64Operand::CreateReg(
4644 Operands.push_back(AArch64Operand::CreateReg(
4659 Operands.push_back(AArch64Operand::CreateReg(
6208 Operands[2] = AArch64Operand::CreateReg(
6371 Operands[2] = AArch64Operand::CreateReg(Re
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonFrameLowering.cpp546 RetI->addOperand(MachineOperand::CreateReg(R.getReg(), false, true));
974 RetI.addOperand(MachineOperand::CreateReg(R.getReg(), false, true));
2571 MI->addOperand(MachineOperand::CreateReg(R.getReg(), IsDef, true, IsKill));
H A DHexagonEarlyIfConv.cpp851 PN->addOperand(MachineOperand::CreateReg(MuxR, false, false, false, false,
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.cpp690 Cond.push_back(MachineOperand::CreateReg(R600::PRED_SEL_ONE, false));
710 Cond.push_back(MachineOperand::CreateReg(R600::PRED_SEL_ONE, false));
H A DAMDGPUInstructionSelector.cpp108 MI.addOperand(*MF, MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
263 return MachineOperand::CreateReg(DstReg, MO.isDef(), MO.isImplicit(),
310 I.addOperand(MachineOperand::CreateReg(AMDGPU::SCC, true, // isDef
347 I.addOperand(*MF, MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
437 I.addOperand(*MF, MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
2943 I.addOperand(*MF, MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp721 return MachineOperand::CreateReg(
809 MOs.push_back(MachineOperand::CreateReg(
/freebsd-current/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInsertVSETVLI.cpp1336 MI.addOperand(MachineOperand::CreateReg(RISCV::VL, /*isDef*/ false,
1339 MI.addOperand(MachineOperand::CreateReg(RISCV::VTYPE, /*isDef*/ false,
H A DRISCVInstrInfo.cpp1250 Cond[1] = MachineOperand::CreateReg(RHS.getReg(), /*isDef=*/false);
1251 Cond[2] = MachineOperand::CreateReg(RegZ, /*isDef=*/false);
1264 Cond[1] = MachineOperand::CreateReg(RegZ, /*isDef=*/false);
1265 Cond[2] = MachineOperand::CreateReg(LHS.getReg(), /*isDef=*/false);
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelDAGToDAG.cpp172 MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true));
179 MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true));
H A DMipsInstrInfo.cpp951 return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
/freebsd-current/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCInstructionSelector.cpp754 MachineOperand::CreateReg(AddrReg, /* isDef */ false,
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp206 Cond.push_back(MachineOperand::CreateReg(Reg, false));
/freebsd-current/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1316 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
1327 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
1384 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
1398 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
2721 MachineOperand::CreateReg(ImpDef, true, true));
2727 MachineOperand::CreateReg(ImpUse, false, true));
5391 Cond.push_back(MachineOperand::CreateReg(
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp900 static std::unique_ptr<MipsOperand> CreateReg(unsigned Index, StringRef Str, function in class:__anon2523::MipsOperand
1519 return CreateReg(Index, Str, RegKind_Numeric, RegInfo, S, E, Parser);
1527 return CreateReg(Index, Str, RegKind_GPR, RegInfo, S, E, Parser);
1535 return CreateReg(Index, Str, RegKind_FGR, RegInfo, S, E, Parser);
1543 return CreateReg(Index, Str, RegKind_HWRegs, RegInfo, S, E, Parser);
1551 return CreateReg(Index, Str, RegKind_FCC, RegInfo, S, E, Parser);
1559 return CreateReg(Index, Str, RegKind_ACC, RegInfo, S, E, Parser);
1567 return CreateReg(Index, Str, RegKind_MSA128, RegInfo, S, E, Parser);
1575 return CreateReg(Index, Str, RegKind_MSACtrl, RegInfo, S, E, Parser);
/freebsd-current/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp8767 MachineOperand SrcBase = MachineOperand::CreateReg(0U, false);
8777 Base = MachineOperand::CreateReg(Reg, false);
8875 return MachineOperand::CreateReg(Reg, false);
8940 MachineOperand::CreateReg(StartDestReg, false), DestDisp,
8941 MachineOperand::CreateReg(StartSrcReg, false), SrcDisp,
8968 DestBase = MachineOperand::CreateReg(NextDestReg, false);
8969 SrcBase = MachineOperand::CreateReg(NextSrcReg, false);
9004 MachineOperand::CreateReg(ThisDestReg, false), DestDisp,
9005 MachineOperand::CreateReg(ThisSrcReg, false), SrcDisp, 256);
9060 MachineOperand::CreateReg(RemDestRe
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