| /freebsd-9.3-release/contrib/llvm/lib/CodeGen/ |
| H A D | PHIElimination.cpp | 260 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
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| H A D | MachineFunction.cpp | 428 assert(MRI.getRegClass(VReg) == RC && "Register class mismatch!");
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| H A D | PrologEpilogInserter.cpp | 828 const TargetRegisterClass *RC = Fn.getRegInfo().getRegClass(Reg);
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| H A D | TargetLoweringBase.cpp | 914 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
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| /freebsd-9.3-release/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.cpp | 584 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
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| H A D | ARMFastISel.cpp | 300 TII.getRegClass(II, OpNum, &TRI, *FuncInfo.MF);
2213 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
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| H A D | ARMLoadStoreOptimizer.cpp | 1834 const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF);
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| H A D | ARMBaseInstrInfo.cpp | 1740 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
2564 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
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| /freebsd-9.3-release/contrib/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXAsmPrinter.cpp | 377 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
624 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
1693 const TargetRegisterClass *RC = MRI->getRegClass(vr);
1712 const TargetRegisterClass *RC = TRI->getRegClass(i);
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| /freebsd-9.3-release/contrib/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 2937 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
2965 MRI.getRegClass(DstReg)->getSize(),
3671 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
4002 unsigned RCSize = getRegClass(MI->getDesc(), i, &RI, MF)->getSize();
4242 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(MO.getReg());
4433 MF.getRegInfo().getRegClass(LoadMI->getOperand(0).getReg())->getSize()
4440 MF.getRegInfo().getRegClass(LoadMI->getOperand(0).getReg())->getSize()
4530 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
4625 const TargetRegisterClass *DstRC = getRegClass(MCI
[all...] |
| H A D | X86FastISel.cpp | 863 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
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| /freebsd-9.3-release/contrib/llvm/lib/Target/ARM/InstPrinter/ |
| H A D | ARMInstPrinter.cpp | 272 const MCRegisterClass& MRC = MRI.getRegClass(ARM::GPRRegClassID);
283 &MRI.getRegClass(ARM::GPRPairRegClassID)));
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| /freebsd-9.3-release/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonVLIWPacketizer.cpp | 556 const TargetRegisterClass* PacketRC = QII->getRegClass(MCID, 0, QRI, MF);
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| H A D | HexagonISelDAGToDAG.cpp | 1231 const TargetRegisterClass *RC = TII->getRegClass(MCID, i, TRI, *MF);
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| /freebsd-9.3-release/contrib/llvm/lib/Target/Mips/Disassembler/ |
| H A D | MipsDisassembler.cpp | 424 return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
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| /freebsd-9.3-release/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCRegisterInfo.cpp | 809 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
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| H A D | PPCISelDAGToDAG.cpp | 199 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) {
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| /freebsd-9.3-release/contrib/llvm/lib/Target/XCore/Disassembler/ |
| H A D | XCoreDisassembler.cpp | 84 return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
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| /freebsd-9.3-release/contrib/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 1084 return *(getContext().getRegisterInfo()->getRegClass(RC).begin() + RegNo);
1089 getContext().getRegisterInfo()->getRegClass(RegClass).getNumRegs())
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| /freebsd-9.3-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGRRList.cpp | 290 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg);
299 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
307 const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI, MF);
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| H A D | FastISel.cpp | 1432 const TargetRegisterClass *RC = MRI.getRegClass(Op0);
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| H A D | SelectionDAGISel.cpp | 553 MRI.constrainRegClass(To, MRI.getRegClass(From));
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| /freebsd-9.3-release/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 2904 RC = TRI->getRegClass(Prefix == "hi" ?
2928 RC = TRI->getRegClass(Mips::MSACtrlRegClassID);
2948 RC = TRI->getRegClass(Mips::FCCRegClassID);
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| /freebsd-9.3-release/contrib/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 301 return Dis->getRegInfo()->getRegClass(RC).getRegister(RegNo);
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| /freebsd-9.3-release/contrib/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.cpp | 1072 CodeGenRegisterClass *CodeGenRegBank::getRegClass(Record *Def) { function in class:CodeGenRegBank
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