| /freebsd-9.3-release/contrib/llvm/lib/CodeGen/ |
| H A D | RegAllocGreedy.cpp | 600 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg)) <
601 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(Intf->reg)));
699 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg.reg);
1044 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
1311 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
1362 if (!RegClassInfo.isProperSubClass(MRI->getRegClass(VirtReg.reg)))
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| H A D | CriticalAntiDepBreaker.cpp | 177 NewRC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
272 NewRC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
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| H A D | MachineCSE.cpp | 136 if (!MRI->constrainRegClass(SrcReg, MRI->getRegClass(Reg)))
545 const TargetRegisterClass *OldRC = MRI->getRegClass(OldReg);
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| H A D | RegAllocPBQP.cpp | 213 const TargetRegisterClass *trc = mri->getRegClass(vreg);
532 const TargetRegisterClass *liRC = mri->getRegClass(li->reg);
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| H A D | MachineLICM.cpp | 782 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
1264 const TargetRegisterClass *RC = TII->getRegClass(MID, LoadRegIndex, TRI, MF);
1358 OrigRCs.push_back(MRI->getRegClass(DupReg));
1360 if (!MRI->constrainRegClass(DupReg, MRI->getRegClass(Reg))) {
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| H A D | MachineSSAUpdater.cpp | 57 VRC = MRI->getRegClass(VR);
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| H A D | RegAllocFast.cpp | 287 const TargetRegisterClass *RC = MRI->getRegClass(LRI->VirtReg);
515 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
625 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
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| H A D | MachineInstr.cpp | 960 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
978 return TRI->getRegClass(RCID);
1550 OS << ':' << TM->getRegisterInfo()->getRegClass(RCID)->getName();
1599 const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1602 if (MRI->getRegClass(VirtRegs[j]) != RC) {
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| H A D | AggressiveAntiDepBreaker.cpp | 387 RC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
461 RC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
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| H A D | MachineVerifier.cpp | 904 TII->getRegClass(MCID, MONum, TRI, *MF)) {
913 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
931 TII->getRegClass(MCID, MONum, TRI, *MF)) {
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| H A D | TwoAddressInstructionPass.cpp | 1198 TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI, *MF));
1323 if (const TargetRegisterClass *RC = TII->getRegClass(MCID, SrcIdx,
1420 MRI->constrainRegClass(RegA, MRI->getRegClass(RegB));
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| H A D | EarlyIfConversion.cpp | 483 unsigned DstReg = MRI->createVirtualRegister(MRI->getRegClass(PHIDst));
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| /freebsd-9.3-release/contrib/llvm/lib/Target/R600/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 125 return TM.getRegisterInfo()->getRegClass(RegClass);
128 const TargetRegisterClass *SuperRC = TM.getRegisterInfo()->getRegClass(
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| H A D | AMDGPUInstrInfo.cpp | 341 const TargetRegisterClass * oldRegClass = MRI.getRegClass(MO.getReg());
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| H A D | SIISelLowering.cpp | 986 return MRI.getRegClass(Reg);
996 return TRI.getRegClass(OpClassID);
1010 return TRI.getRegClass(OpClassID);
1019 return TRI.getRegClass(
1034 return TRI->getRegClass(RegClass)->hasSubClassEq(RC);
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| H A D | R600MachineScheduler.cpp | 215 return MRI->getRegClass(Reg) == RC;
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| /freebsd-9.3-release/contrib/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 399 const MCRegisterClass& getRegClass(unsigned i) const {
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| /freebsd-9.3-release/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 443 (ResultReg ? MRI.getRegClass(ResultReg) :
560 AssignedReg ? MRI.getRegClass(AssignedReg) : 0;
575 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg);
1010 AssignedReg ? MRI.getRegClass(AssignedReg) : 0;
1044 const TargetRegisterClass *InRC = MRI.getRegClass(SrcReg);
1094 (AssignedReg ? MRI.getRegClass(AssignedReg) :
1725 (AssignedReg ? MRI.getRegClass(AssignedReg) :
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| /freebsd-9.3-release/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonHardwareLoops.cpp | 766 const TargetRegisterClass *RC = MRI->getRegClass(R);
1234 const TargetRegisterClass *RC = MRI->getRegClass(R);
1465 const TargetRegisterClass *RC = MRI->getRegClass(PR);
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| /freebsd-9.3-release/contrib/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.cpp | 699 MRI.getRegClass(DestReg)->contains(SystemZ::R1L) &&
700 MRI.getRegClass(SrcReg)->contains(SystemZ::R1L)) {
773 .getRegClass(MI->getOperand(OpNum).getReg())->getSize() &&
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| /freebsd-9.3-release/contrib/llvm/include/llvm/Target/ |
| H A D | TargetInstrInfo.h | 58 /// getRegClass - Givem a machine instruction descriptor, returns the register
60 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID,
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| H A D | TargetRegisterInfo.h | 557 /// getRegClass - Returns the register class associated with the enumeration
559 const TargetRegisterClass *getRegClass(unsigned i) const {
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| /freebsd-9.3-release/contrib/llvm/lib/Target/ARM/ |
| H A D | MLxExpansionPass.cpp | 290 TII->getRegClass(MCID1, 0, TRI, MF));
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| /freebsd-9.3-release/contrib/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.h | 614 CodeGenRegisterClass *getRegClass(Record*);
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| /freebsd-9.3-release/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 432 unsigned DstRegSize = getRegClass(Desc, 0, RI, MF)->getSize();
433 unsigned SrcRegSize = getRegClass(Desc, 1, RI, MF)->getSize();
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