Searched refs:x7 (Results 201 - 225 of 833) sorted by relevance

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/freebsd-13-stable/sys/dev/ath/ath_hal/
H A Dah_eeprom_v14.h52 #define AR5416_EEP_MINOR_VER_7 0x7
92 #define AR5416_ANT_CHAIN_MASK 0x7
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/
H A DAsmPrinterDwarf.cpp191 if ((Encoding & 0x7) == dwarf::DW_EH_PE_uleb128)
199 if ((Encoding & 0x7) == dwarf::DW_EH_PE_uleb128)
/freebsd-13-stable/sys/dev/vt/hw/fb/
H A Dvt_early_fb.c98 0x7, 5, 0x7, 2, 0x3, 0);
/freebsd-13-stable/sys/netgraph/bluetooth/include/
H A Dng_btsocket_rfcomm.h85 #define RFCOMM_RPN_BR_115200 0x7
103 #define RFCOMM_RPN_PARITY_SPACE 0x7
/freebsd-13-stable/sys/powerpc/pseries/
H A Drtas_pci.c161 ((func & 0x7) << 8) | (reg & 0xff);
200 ((func & 0x7) << 8) | (reg & 0xff);
/freebsd-13-stable/sys/dev/cxgb/common/
H A Dcxgb_mv88e1xxx.c79 #define M_DOWNSHIFT_CNT 0x7
105 #define M_PSSR_CABLE_LEN 0x7
/freebsd-13-stable/sys/dev/mge/
H A Dif_mgevar.h311 #define MGE_ENABLE_RXQ(q) (1 << ((q) & 0x7))
313 #define MGE_DISABLE_RXQ(q) (1 << (((q) & 0x7) + 8))
/freebsd-13-stable/sys/amd64/vmm/amd/
H A Damdvi_priv.h127 #define AMDVI_COMP_PPR_OPCODE 0x7 /* Complete PPR request. */
169 #define AMDVI_EVENT_IOTLB_TIMEOUT 0x7
/freebsd-13-stable/sys/arm/allwinner/
H A Daw_usb3phy.c67 #define PTH_LOS_BIAS (0x7 << 3)
68 #define PTH_TX_BOOST_LVL (0x7 << 0)
/freebsd-13-stable/sys/arm/nvidia/
H A Dtegra_mc.c73 #define MC_ERR_TYPE(x) (((x) >> 28) & 0x7)
85 #define MC_ERR_ADR1(x) (((x) >> 12) & 0x7)
/freebsd-13-stable/sys/arm64/arm64/
H A Dexception.S54 stp x6, x7, [sp, #(TF_X + 6 * 8)]
118 ldp x6, x7, [sp, #(TF_X + 6 * 8)]
/freebsd-13-stable/sys/arm64/freescale/imx/clk/
H A Dimx_clk_composite.c47 #define TARGET_ROOT_PRE_PODF(n) ((((n) - 1) & 0x7) << 16)
48 #define TARGET_ROOT_PRE_PODF_MASK (0x7 << 16)
/freebsd-13-stable/sys/cddl/dev/dtrace/riscv/
H A Ddtrace_subr.c283 uimm = ((invop >> 10) & 0x7) << 3;
284 uimm |= ((invop >> 7) & 0x7) << 6;
/freebsd-13-stable/sys/contrib/device-tree/src/arm/
H A Dimx6ull-pinfunc.h18 #define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00C0 0x034C 0x0644 0x0 0x7
24 #define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01EC 0x0478 0x0640 0x8 0x7
H A Dimx6sl-pinfunc.h636 #define MX6SL_PAD_LCD_DAT0__SRC_BOOT_CFG00 0x1b0 0x4b8 0x000 0x7 0x0
644 #define MX6SL_PAD_LCD_DAT1__SRC_BOOT_CFG01 0x1b4 0x4bc 0x000 0x7 0x0
652 #define MX6SL_PAD_LCD_DAT10__SRC_BOOT_CFG10 0x1b8 0x4c0 0x000 0x7 0x0
660 #define MX6SL_PAD_LCD_DAT11__SRC_BOOT_CFG11 0x1bc 0x4c4 0x000 0x7 0x0
669 #define MX6SL_PAD_LCD_DAT12__SRC_BOOT_CFG12 0x1c0 0x4c8 0x000 0x7 0x0
678 #define MX6SL_PAD_LCD_DAT13__SRC_BOOT_CFG13 0x1c4 0x4cc 0x000 0x7 0x0
687 #define MX6SL_PAD_LCD_DAT14__SRC_BOOT_CFG14 0x1c8 0x4d0 0x000 0x7 0x0
696 #define MX6SL_PAD_LCD_DAT15__SRC_BOOT_CFG15 0x1cc 0x4d4 0x000 0x7 0x0
704 #define MX6SL_PAD_LCD_DAT16__SRC_BOOT_CFG24 0x1d0 0x4d8 0x000 0x7 0x0
712 #define MX6SL_PAD_LCD_DAT17__SRC_BOOT_CFG25 0x1d4 0x4dc 0x000 0x7
[all...]
/freebsd-13-stable/sys/contrib/alpine-hal/
H A Dal_hal_unit_adapter_regs.h152 #define AL_PCI_MSIX_TABLE_BAR 0x7 /* MSIX table BAR */
156 #define AL_PCI_MSIX_PBA_BAR 0x7 /* MSIX pba BAR */
/freebsd-13-stable/sys/xen/interface/
H A Dtrace.h251 #define TRC_HVM_EMUL_RTC_STOP_TIMER (TRC_HVM_EMUL + 0x7)
275 #define TRC_HW_IRQ_UNMAPPED_VECTOR (TRC_HW_IRQ + 0x7)
/freebsd-13-stable/sys/dev/cxgbe/firmware/
H A Dt4fw_interface.h90 FW_MEMTYPE_HMA = 0x7,
612 #define M_FW_FILTER2_WR_NATMODE 0x7
657 #define M_FW_FILTER_WR_PORT 0x7
663 #define M_FW_FILTER_WR_PORTM 0x7
669 #define M_FW_FILTER_WR_MATCHTYPE 0x7
675 #define M_FW_FILTER_WR_MATCHTYPEM 0x7
1205 FW_RI_TERMINATE = 0x7,
1684 #define M_FW_RI_RES_WR_FBMIN 0x7
1690 #define M_FW_RI_RES_WR_FBMAX 0x7
1703 #define M_FW_RI_RES_WR_CIDXFTHRESH 0x7
[all...]
/freebsd-13-stable/sys/dev/mlx/
H A Dmlxreg.h519 mc->mc_mailbox[0x7] = f3;
545 mc->mc_mailbox[0x7] = f6;
570 mc->mc_mailbox[0x7] = f5;
592 mc->mc_mailbox[0x7] = (f2 >> 24) & 0xff;
615 mc->mc_mailbox[0x7] = (f3 >> 24) & 0xff;
/freebsd-13-stable/sys/ofed/drivers/infiniband/core/
H A Dcm_msgs.h172 switch (req_msg->offset51 & 0x7) {
241 return (u8) (be32_to_cpu(req_msg->offset44) & 0x7);
247 req_msg->offset44 = cpu_to_be32((retry_count & 0x7) |
263 return req_msg->offset50 & 0x7;
270 (rnr_retry_count & 0x7));
/freebsd-13-stable/sys/crypto/openssl/aarch64/
H A Dchacha-armv8.S207 add x7,x7,x8,lsl#32
221 rev x7,x7
230 eor x7,x7,x8
238 stp x5,x7,[x0,#0] // store output
269 add x7,x7,x8,lsl#32
278 rev x7,x
[all...]
/freebsd-13-stable/usr.sbin/ancontrol/
H A Dancontrol.c666 if ((cfg->an_opmode & 0x7) == AN_OPMODE_IBSS_ADHOC)
668 if ((cfg->an_opmode & 0x7) == AN_OPMODE_INFRASTRUCTURE_STATION)
670 if ((cfg->an_opmode & 0x7) == AN_OPMODE_AP)
672 if ((cfg->an_opmode & 0x7) == AN_OPMODE_AP_REPEATER)
676 if ((cfg->an_rxmode & 0x7) == AN_RXMODE_BC_MC_ADDR)
678 if ((cfg->an_rxmode & 0x7) == AN_RXMODE_BC_ADDR)
680 if ((cfg->an_rxmode & 0x7) == AN_RXMODE_ADDR)
682 if ((cfg->an_rxmode & 0x7) == AN_RXMODE_80211_MONITOR_CURBSS)
684 if ((cfg->an_rxmode & 0x7) == AN_RXMODE_80211_MONITOR_ANYBSS)
686 if ((cfg->an_rxmode & 0x7)
[all...]
/freebsd-13-stable/sys/dev/qlnx/qlnxe/
H A Dcommon_hsi.h901 #define DB_L2_DPM_DATA_SGE_NUM_MASK 0x7 /* In DPM_L2_BD mode: the number of SGE-s */
934 #define DB_LEGACY_ADDR_DEMS_MASK 0x7 /* doorbell extraction mode specifier- 0 if not used */
946 #define DB_PWM_ADDR_RESERVED0_MASK 0x7
1171 #define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK 0x7 /* port number. Only when part of ME register. */
1284 #define RDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7 /* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8KB */
1404 #define TDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7 /* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8KB */
1485 #define TIMERS_CONTEXT_RESERVED7_MASK 0x7
/freebsd-13-stable/sys/mips/cavium/cryptocteon/
H A Dcavium_crypto.c337 (crypt_off & 0x7) || (crypt_off + crypt_len > iovlen))) {
405 (crypt_off & 0x7) || (crypt_off + crypt_len > iovlen))) {
478 (auth_off & 0x7) || (auth_off + auth_len > iovlen))) {
586 (crypt_len & 0x7) ||
587 (auth_len & 0x7) ||
777 (crypt_len & 0x7) ||
778 (auth_len & 0x7) ||
/freebsd-13-stable/sys/dev/cxgbe/tom/
H A Dt4_tls.h382 #define M_TLS_KEYCTX_TX_WR_HMACCTRL 0x7
455 #define M_TLS_KEYCTX_TX_WR_RXCK_SIZE 0x7
463 #define M_TLS_KEYCTX_TX_WR_RXMK_SIZE 0x7

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