Searched refs:isUse (Results 26 - 50 of 108) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DExpandPostRAPseudos.cpp80 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
H A DLivePhysRegs.cpp95 assert(O->isUse());
H A DMachineCSE.cpp169 if (!MO.isReg() || !MO.isUse())
242 if (MO.isUse())
467 if (MO.isReg() && MO.isUse() && Register::isVirtualRegister(MO.getReg())) {
H A DRegisterScavenging.cpp141 if (MO.isUse()) {
211 if (MO.isUse()) {
545 if (MO.isReg() && MO.getReg() != 0 && !(MO.isUse() && MO.isUndef()) &&
H A DMachineLICM.cpp1067 if (MO.isUse()) {
1088 if (!MO.isUse())
1154 if (!MO.isReg() || !MO.isUse())
H A DTargetInstrInfo.cpp632 assert(MI.getOperand(OpIdx).isUse() && "Folding load into def!");
942 if (MO.isUse()) {
963 if (MO.isUse())
H A DBranchFolding.cpp1812 if (MO.isUse()) {
1844 if (!MO.isReg() || MO.isUse())
1877 if (MO.isUse()) {
1995 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
H A DExecutionDomainFix.cpp244 if (MO.isUse())
H A DInlineSpiller.cpp571 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg)
636 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) {
864 if (MO->isUse())
1060 if (MO.isUse()) {
H A DMachineCopyPropagation.cpp456 MIUse.isUse() && TRI->regsOverlap(Use.getReg(), MIUse.getReg()))
756 if (!MODef.isReg() || MODef.isUse())
H A DMachinePipeliner.cpp868 } else if (MOI->isUse()) {
1630 if (MO.isReg() && MO.isUse()) {
2587 } else if (MO.isUse() && Writes && stageScheduled(*I) == StageInst1) {
2596 } else if (MO.isUse() && Writes && stageScheduled(*I) > StageInst1) {
2604 } else if (MO.isUse() && Writes && stageScheduled(*I) < StageInst1) {
2609 } else if (MO.isUse() && stageScheduled(*I) == StageInst1 &&
2862 if (MO.isReg() && MO.isUse() && MO.getReg() == OverlapReg) {
H A DMachineCombiner.cpp181 if (!MO.isUse())
H A DReachingDefAnalysis.cpp29 return isValidReg(MO) && MO.isUse();
H A DVirtRegMap.cpp542 if (MO.isUse()) {
H A DDetectDeadLanes.cpp467 if (!MO.isUse())
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineOperand.h368 bool isUse() const { function
458 return !isUndef() && !isInternalRead() && (isUse() || getSubReg());
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNRegPressure.cpp215 assert(MO.isUse() && MO.isReg() && Register::isVirtualRegister(MO.getReg()));
238 if (!MO.isUse() || !MO.readsReg())
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp191 if ((!MO.isReg()) || (!MO.isUse()))
403 if (!MO.isReg() || !MO.isUse())
H A DThumb2SizeReduction.cpp301 if (!MO.isReg() || MO.isUndef() || MO.isUse())
985 if (!MO.isReg() || MO.isUndef() || MO.isUse())
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenMux.cpp371 if (!Op.isReg() || !Op.isUse())
H A DHexagonVLIWPacketizer.cpp590 if (MO.isReg() && MO.isUse() && DefRegsSet.count(MO.getReg()))
812 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == DepReg)
956 if (Op.isReg() && Op.getReg() && Op.isUse() &&
H A DHexagonBlockRanges.cpp321 if (!Op.isReg() || !Op.isUse() || Op.isUndef())
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCBranchCoalescing.cpp353 && !(Op1.isUse() && MRI->isConstantPhysReg(Op1.getReg()))) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CollectLOH.cpp548 assert(Op.isReg() && Op.isUse() && "Expected reg use");
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCOptAddrMode.cpp407 if (!O.isReg() || !O.isUse())

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