Searched refs:isReg (Results 226 - 250 of 347) sorted by relevance

1234567891011>>

/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSILowerControlFlow.cpp395 if (MI.getOperand(1).isReg()) {
522 if (!Op.isReg() || !Register::isVirtualRegister(Op.getReg())) {
541 if (SrcOp.isReg() && SrcOp.isUse() &&
H A DSIWholeQuadMode.cpp274 if (!Use.isReg() || !Use.isUse())
361 if (Inactive.isReg()) {
391 if (!MO.isReg())
H A DSILoadStoreOptimizer.cpp170 if (!AddrOp->isReg())
604 if (Op.isReg()) {
636 if (Use.isReg() &&
1716 if (!Op.isReg())
1739 if (!Base.isReg())
1749 if (!BaseLo.isReg() || !BaseHi.isReg())
H A DSIInstrInfo.h691 return MO.isReg() && RI.isVGPR(MRI, MO.getReg());});
834 if (MO.isReg()) {
1072 assert(O.isReg());
H A DR600OptimizeVectorRegisters.cpp300 if (!MOp->isReg())
H A DSIInsertSkips.cpp328 assert(MI.getOperand(0).isReg());
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FlagsCopyLowering.cpp395 assert(VOp.isReg() &&
742 MI.getOperand(0).isReg() &&
966 assert(SetCCI.getOperand(0).isReg() &&
H A DX86InstrInfo.cpp681 MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
1084 if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
1086 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
1105 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
1107 !MI.getOperand(1 + X86::AddrDisp).isReg()) {
1109 if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
1159 if (MO.isReg() && MO.isDef() &&
1396 if (MI.getOperand(2).isReg() && MI.getOperand(2).isUndef())
2616 if (!MI.getOperand(SrcOpIdx1).isReg() ||
2617 !MI.getOperand(SrcOpIdx2).isReg())
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp243 bool isReg() const override {
365 return isReg() || isImm();
2027 assert(R->isReg());
2494 assert(R->isReg());
2885 } else if (MO.isReg()) {
2929 if (MO.isReg()) {
2991 assert(Dst.isReg());
2999 if (Src.isReg()) {
3163 if (!Src0.isReg())
3182 if (!Src0.isReg())
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp199 if (!MO.isReg())
639 if (Cond[2].isReg()) {
1608 if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1648 if (MO.isReg()) {
2649 if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg())
2654 if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() &&
2976 if (!BaseOp || !BaseOp->isReg())
2987 if (Op.isReg() && Op.isUse() && Op.getReg() == Hexagon::R29)
2997 if (!Stored.isReg())
[all...]
H A DHexagonBitTracker.cpp169 if (MO.isReg())
196 if (!MO.isReg() || !MO.isDef())
271 if (!Op.isReg())
1043 if (!Op.isReg() || !Op.isDef())
1190 assert(MD.isReg() && MD.isDef());
H A DHexagonBitSimplify.cpp292 if (!Op.isReg() || !Op.isDef())
304 if (!Op.isReg() || !Op.isUse())
1017 if (!Op.isReg() || !Op.isDef())
1259 assert(MI.getOperand(OpN).isReg());
1327 if (!Op.isReg())
1960 if (!MI->getOperand(0).isReg())
2147 if (!Op.isReg())
2730 if (!Op0.isReg() || !Op0.isDef())
3019 if (!Op.isReg())
3096 if (!Op.isReg()) {
[all...]
H A DHexagonGenInsert.cpp613 if (MO.isReg() && MO.isDef()) {
730 if (!MO.isReg() || !MO.isDef())
743 if (!MO.isReg() || !MO.isUse())
1483 if (!MO.isReg() || !MO.isDef())
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DRDFGraph.cpp609 assert(Op.isReg());
976 assert(Op.isReg() || Op.isRegMask());
977 if (Op.isReg())
1274 if (!Op.isReg() || Op.getReg() == 0 || !Op.isUse() || Op.isUndef())
1294 if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1339 if (!Op.isReg() || !Op.isDef() || !Op.isImplicit())
1368 if (!Op.isReg() || !Op.isUse())
H A DMachineTraceMetrics.cpp662 if (!MO.isReg())
710 if (!MO.isReg())
904 if (!MO.isReg())
H A DShrinkWrap.cpp278 if (MO.isReg()) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp101 if (EarlierMI->getOperand(0).isReg() && EarlierMI->getOperand(0).isUse())
521 if (MI.getNumExplicitOperands() == 2 && MI.getOperand(0).isReg() &&
980 if (Op.isReg() && Op.isKill())
1303 if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
1827 assert(MBBI->isCompare() && MBBI->getOperand(0).isReg() &&
1828 MBBI->getOperand(1).isReg() && !MBBI->mayLoad() &&
1949 ((MCOI.RegClass != -1 && !Op.isReg() && !Op.isFI()) ||
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp280 if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
577 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
588 if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead())
606 assert(Offset.isReg());
711 if (!MO.isReg() || MO.isUndef() || MO.isUse())
1264 if (MI.getOperand(1).isFI() && MI.getOperand(2).isReg() &&
1501 if (MI.getOperand(1).isFI() && MI.getOperand(2).isReg() &&
2253 if (!MO.isReg())
2516 if (MO.isReg() && !MO.isImplicit() &&
2847 OI->getOperand(0).isReg()
[all...]
H A DThumb1FrameLowering.cpp644 if (MO.isReg() && (MO.isImplicit() || MO.isDef()))
759 if (MO.isReg() && (MO.isImplicit() || MO.isDef()) &&
977 if (Op.isReg())
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp1340 bool isReg() const override { return Kind == k_Register; }
4048 if (!PrevOp->isReg())
6518 if (!Op3.isReg() || !Op4.isReg())
6533 (Op5.isReg() && Op5.getReg() == ARM::PC);
6536 (Op5.isReg() && Op5.getReg() == ARM::SP)) &&
6561 if (!Transform && Op5.isReg() && Op3Reg == Op5.getReg() &&
6576 LastOp->isReg())
6614 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6615 static_cast<ARMOperand &>(*Operands[4]).isReg()
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp632 if ((MIb.getNumOperands() > 1) && MIb.getOperand(1).isReg() &&
635 if ((MIb.getNumOperands() > 0) && MIb.getOperand(0).isReg() &&
663 if (Inst.getOperand(opNum).isReg()) {
H A DHexagonMCInstrInfo.cpp391 MCO.isReg());
411 MCO.isReg());
757 return Inst.getOperand(I).isReg() &&
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCSEInfo.cpp371 if (MO.isReg()) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrInfo.cpp438 if (!MI.getOperand(BasePos).isReg() || !MI.getOperand(OffsetPos).isImm())
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZMCCodeEmitter.cpp175 if (MO.isReg())

Completed in 774 milliseconds

1234567891011>>