Lines Matching refs:isReg
1340 bool isReg() const override { return Kind == k_Register; }
4048 if (!PrevOp->isReg())
6518 if (!Op3.isReg() || !Op4.isReg())
6533 (Op5.isReg() && Op5.getReg() == ARM::PC);
6536 (Op5.isReg() && Op5.getReg() == ARM::SP)) &&
6561 if (!Transform && Op5.isReg() && Op3Reg == Op5.getReg() &&
6576 LastOp->isReg())
6614 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6615 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
6624 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6625 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
6628 ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) ||
6637 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6638 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
6666 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6667 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
6668 static_cast<ARMOperand &>(*Operands[5]).isReg() &&
6686 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6687 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
6703 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6719 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6752 if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() &&
6779 ((*Operand).isReg() &&
6794 (Operand->isReg() &&
6841 if (!Op2.isReg())
6887 if (!Op2.isReg())
6922 if (!Op3.isReg() || Op3.getReg() != RNext)
7305 if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) &&
7335 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
7337 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
8035 if (Inst.getOperand(i).isReg() &&
10597 if (Inst.getOperand(0).isReg() && Inst.getOperand(0).getReg() == ARM::SP &&
10609 if (!Op.isReg()) {
12181 if (hasV8Ops() && Op.isReg() && Op.getReg() == ARM::SP)
12185 if (Op.isReg() &&