Searched refs:isReg (Results 201 - 225 of 347) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMAsmPrinter.cpp287 if (MI->getOperand(OpNum).isReg()) {
312 if (!MI->getOperand(OpNum).isReg())
333 while (MI->getOperand(RegOps).isReg()) {
388 if (!MO.isReg())
402 if (!MO.isReg())
411 if (!MI->getOperand(OpNum).isReg())
428 if (!MO.isReg())
457 if (!MI->getOperand(OpNum).isReg())
465 assert(MO.isReg() && "unexpected inline asm memory operand");
1519 if (MI->getOperand(1).isReg()) {
[all...]
H A DARMLowOverheadLoops.cpp571 return MO.isReg() && MO.getReg() && Class->contains(MO.getReg());
641 if (!MO.isReg() || !MO.getReg())
719 !Copy->getOperand(1).isReg() || !Copy->getOperand(2).isReg() ||
992 if (!MO.isReg() || MO.getReg() != ARM::VPR)
1376 if (MO.isReg() && MO.isUse() && MO.isTied() &&
H A DMVEVPTOptimisationsPass.cpp134 if (!Dst.isReg())
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonEarlyIfConv.cpp386 if (!MO.isReg() || !MO.isDef())
403 if (!MO.isReg() || !MO.isUse())
474 assert(RA.isReg() && RB.isReg());
493 if (!MO.isReg() || !MO.isDef())
H A DHexagonBlockRanges.cpp321 if (!Op.isReg() || !Op.isUse() || Op.isUndef())
337 if (!Op.isReg() || !Op.isDef() || Op.isUndef())
H A DHexagonGenPredicate.cpp355 if (MO.isReg() && MO.isUse())
376 if (!MO.isReg() || !MO.isUse())
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DModuloSchedule.cpp80 if (!Op.isReg() || !Op.isDef())
627 if (!MO.isReg() || !MO.isDef() ||
729 if (!MOI->isReg() || !MOI->isDef())
925 if (!BaseOp->isReg())
993 if (MO.isReg() && MO.isUse())
1034 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
1327 if (!MO.isReg() || MO.getReg().isPhysical() || MO.isImplicit())
1573 return MO->isReg() && MO->getReg().isVirtual() &&
1692 if (!MO.isReg())
H A DInlineSpiller.cpp549 if (MO.isReg() && MO.getReg() == VReg)
571 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg)
636 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) {
857 if (!MO->isReg())
896 if (!MO.isReg() || !MO.isImplicit())
1532 if (MO.isReg() && MO.isImplicit() && MO.isDef() && !MO.isDead())
H A DMachineRegisterInfo.cpp238 if (!MO->isReg()) {
351 if (Src->isReg()) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86MCInstLower.cpp321 assert(Inst.getOperand(0).isReg() &&
323 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
376 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
381 Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
382 Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() &&
384 Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() &&
385 Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() &&
1497 assert(Op->isReg() && "Only support arguments in registers");
1595 assert(Op->isReg()
[all...]
H A DX86CallLowering.cpp399 unsigned CallOpc = Info.Callee.isReg()
450 if (Info.Callee.isReg())
H A DX86ExpandPseudo.cpp90 if (Selector.isReg())
291 assert(DestAddr.isReg() && "Offset should be in register!");
H A DX86FixupBWInsts.cpp261 if (!MO.isReg())
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp496 else if (Root.isReg()) {
526 if (!MO.isReg()) {
1063 if (!MI->getOperand(0).isReg() ||
1870 I.getOperand(0).isReg() ? MRI.getType(I.getOperand(0).getReg()) : LLT{};
3449 assert(LaneIdxOp.isReg() && "Lane index operand was not a register?");
3716 assert(LHS.isReg() && RHS.isReg() && "Expected LHS and RHS to be registers!");
3740 assert(LHS.isReg() && RHS.isReg() && "Expected LHS and RHS to be registers!");
3795 assert(LHS.isReg()
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/MSP430/AsmParser/
H A DMSP430AsmParser.cpp159 bool isReg() const override { return Kind == k_Reg; }
584 if (!Op.isReg())
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips16InstrInfo.cpp356 if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&
372 if (MO.isReg() && MO.isDef()) {
H A DMicroMipsSizeReduction.cpp287 if (MO.isReg() && ((MO.getReg() == Mips::SP)))
294 if (MO.isReg() && Mips::GPRMM16RegClass.contains(MO.getReg()))
301 if (MO.isReg() && Mips::GPRMM16ZeroRegClass.contains(MO.getReg()))
H A DMipsAsmPrinter.cpp578 if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) {
603 if (!MO.isReg())
630 assert(BaseMO.isReg() &&
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/
H A DAsmPrinterInlineAsm.cpp499 for (; MI->getOperand(NumDefs).isReg() && MI->getOperand(NumDefs).isDef();
650 if (MO.isReg()) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64A57FPLoadBalancing.cpp554 if (U.isReg() && U.isUse() && Substs.find(U.getReg()) != Substs.end()) {
687 if (MO.isReg()) {
H A DAArch64CondBrTuning.cpp94 if (MO.isReg() && MO.isDead() && MO.getReg() == AArch64::NZCV)
H A DAArch64SLSHardening.cpp348 if (!Op.isReg())
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DSIMCCodeEmitter.cpp393 if (MO.isReg()) {
482 if (MO.isReg())
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyInstPrinter.cpp223 if (Op.isReg()) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DRegBankSelect.cpp240 assert(MO.isReg() && "We should only repair register operand");
470 if (!MO.isReg())
739 assert(MO.isReg() && "Trying to repair a non-reg operand");

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