Searched refs:isReg (Results 176 - 200 of 347) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveVariables.cpp216 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
521 if (!MO.isReg() || MO.getReg() == 0)
692 if (MO.isReg() && MO.isKill()) {
785 if (I->isReg() && Register::isVirtualRegister(I->getReg())) {
H A DMachineLoopUtils.cpp76 if (MO.isReg() && Remaps.count(MO.getReg()))
H A DLiveDebugValues.cpp177 return MI.getDebugOperand(0).isReg() ? MI.getDebugOperand(0).getReg()
187 if (!Op.isReg())
1024 if (!MI.getDebugOperand(0).isReg() ||
1106 assert(MI.getDebugOperand(0).isReg() &&
1238 if (MO.isReg() && MO.isDef() && MO.getReg() &&
1307 if (!MO.isReg() || !MO.isUse()) {
1765 if (MO.isReg() && MO.isDef() && MO.getReg())
H A DBranchFolding.cpp800 if (MO.isReg() && MO.isUndef()) {
1807 if (!MO.isReg())
1844 if (!MO.isReg() || MO.isUse())
1872 if (!MO.isReg())
1945 if (!MO.isReg())
1995 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
2013 if (!MO.isReg() || !MO.isDef() || MO.isDead())
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonOptAddrMode.cpp134 if (StOp.isReg() && StOp.getReg() == TfrDefR)
201 if (UseMID.mayStore() && UseMI.getOperand(2).isReg() &&
366 if (!BaseOp.isReg() || BaseOp.getReg() != AddDefR)
758 if (op.isReg() && op.isUse() && DefR == op.getReg())
H A DRDFDeadCode.cpp67 if (Op.isReg() && MRI.isReserved(Op.getReg()))
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp112 if (Instr.getOperand(2).isReg()) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiAsmPrinter.cpp134 if (!MO.isReg())
H A DLanaiInstrInfo.cpp364 if (!MO.isReg() || MO.getReg() != Lanai::SR)
476 if (!MO.isReg())
764 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm() ||
792 if (!BaseOp->isReg())
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/MCTargetDesc/
H A DNVPTXInstPrinter.cpp87 if (Op.isReg()) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DRegisterBankInfo.cpp186 if (!MO.isReg())
235 if (!MO.isReg())
448 if (!MO.isReg()) {
611 if (!MO.isReg()) {
H A DCombinerHelper.cpp377 assert(LoadValue.isReg() && "Result wasn't a register?");
1534 return MO.isReg() &&
1541 return !MO.isReg() ||
1565 if (!MOP1.isReg() || !MOP2.isReg())
1614 return MO.isReg() && MO.getReg().isPhysical();
1636 if (!MOP.isReg())
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64DeadRegisterDefinitionsPass.cpp144 if (!MO.isReg() || !MO.isDef())
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DR600MCCodeEmitter.cpp175 if (MO.isReg()) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFixupVectorISel.cpp94 if (!WOp->isReg() || !Register::isVirtualRegister(WOp->getReg()))
H A DSIInsertWaitcnts.cpp479 assert(Op.isReg());
577 if (Op.isReg() && !Op.isDef() && TRI->isVGPR(*MRI, Op.getReg())) {
624 if (DefMO.isReg() && DefMO.isDef() &&
633 if (MO.isReg() && !MO.isDef() && TRI->isVGPR(*MRI, MO.getReg())) {
654 if (!Op.isReg() || !Op.isDef())
1023 if (!Op.isReg())
1399 Inst.getOperand(0).isReg() &&
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZInstPrinter.cpp44 if (MO.isReg()) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.h129 bool isIndirect() { return Target != nullptr && Target->isReg(); }
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyMCCodeEmitter.cpp86 if (MO.isReg()) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86EvexToVex.cpp131 if (!MO.isReg())
H A DX86InstrBuilder.h96 if (Op0.isReg()) {
H A DX86LoadValueInjectionLoadHardening.cpp397 assert(UseMO.isReg());
798 return (BaseMO.isReg() && BaseMO.getReg() != X86::NoRegister &&
800 (IndexMO.isReg() && IndexMO.getReg() != X86::NoRegister &&
809 if (Use.isReg() && Use.getReg() == Reg)
H A DX86VZeroUpper.cpp162 if (!MO.isReg())
H A DX86WinAllocaExpander.cpp83 assert(MI->getOperand(0).isReg());
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp555 if (MO.isReg()) {
721 if (MCOp1.isImm() && MCOp2.isReg() &&
982 if (!MO.isReg()) {
1115 if (!MO.isReg()) {
1286 bool isReg = MO.getReg() != 0;
1289 if (isReg) {
1295 return Binary | (isAdd << 12) | (isReg << 13);
1344 if (!MO.isReg()) {
1420 if (!MO.isReg()) {
1460 if (!MO.isReg()) {
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