Searched refs:clock (Results 76 - 100 of 371) sorted by relevance

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/freebsd-13-stable/contrib/unbound/sldns/
H A Dparseutil.c147 sldns_gmtime64_r(int64_t clock, struct tm *result) argument
150 result->tm_sec = (int) LDNS_MOD(clock, 60);
151 clock = LDNS_DIV(clock, 60);
152 result->tm_min = (int) LDNS_MOD(clock, 60);
153 clock = LDNS_DIV(clock, 60);
154 result->tm_hour = (int) LDNS_MOD(clock, 24);
155 clock = LDNS_DIV(clock, 2
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/freebsd-13-stable/contrib/ldns/
H A Dutil.c275 ldns_gmtime64_r(int64_t clock, struct tm *result) argument
278 result->tm_sec = (int) LDNS_MOD(clock, 60);
279 clock = LDNS_DIV(clock, 60);
280 result->tm_min = (int) LDNS_MOD(clock, 60);
281 clock = LDNS_DIV(clock, 60);
282 result->tm_hour = (int) LDNS_MOD(clock, 24);
283 clock = LDNS_DIV(clock, 2
[all...]
/freebsd-13-stable/sys/dev/drm2/
H A Ddrm_modes.c53 mode->base.id, mode->name, mode->vrefresh, mode->clock,
259 /* 15/13. Find pixel clock frequency (kHz for xf86) */
260 drm_mode->clock = drm_mode->htotal * HV_FACTOR * 1000 / hperiod;
261 drm_mode->clock -= drm_mode->clock % CVT_CLOCK_STEP;
425 /* 21.Find pixel clock frequency: */
450 drm_mode->clock = pixel_freq;
606 calc_val = (mode->clock * 1000) / mode->htotal; /* hsync in Hz */
641 calc_val = (mode->clock * 1000);
773 /* do clock chec
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/freebsd-13-stable/contrib/sendmail/libsm/
H A Dfpos.c22 #include <sm/clock.h>
H A Dt-event.c22 #include <sm/clock.h>
H A Dfclose.c26 #include <sm/clock.h>
/freebsd-13-stable/sys/dev/twa/
H A Dtw_osl_share.h51 #include <sys/clock.h>
/freebsd-13-stable/sys/x86/x86/
H A Ddelay.c35 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
50 #include <machine/clock.h>
/freebsd-13-stable/contrib/llvm-project/compiler-rt/lib/tsan/rtl/
H A Dtsan_clock.cpp18 // ThreadClock contains fixed-size vector clock for maximum number of threads.
19 // SyncClock contains growable vector clock for currently necessary number of
25 // clock[i] = max(clock[i], src->clock[i]);
30 // dst->clock[i] = max(dst->clock[i], clock[i]);
35 // tmp = clock[i];
36 // clock[
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/freebsd-13-stable/sys/mips/mediatek/
H A Dmtk_spi_v1.c251 uint32_t cs, clock, mode; local
258 spibus_get_clock(child, &clock);
286 if (clock != 0) {
287 div = (mtk_soc_get_cpuclk() + (clock - 1)) / clock;
/freebsd-13-stable/sys/dev/bhnd/cores/pmu/
H A Dbhnd_pmu_subr.c348 /* d11 slow to fast clock transition time in slow clock cycles */
1146 /* setup pll and query clock speed */
1176 /* setup pll and query clock speed */
1451 /* query alp/xtal clock frequency */
1550 /* Wait for HT clock to shutdown. */
1599 /* query alp/xtal clock frequency */
1620 /* query CPU clock frequency */
1664 /* Return ARM/SB clock */
1735 /* Wait for HT clock t
2150 uint32_t clock; local
2289 uint32_t chipst, clock; local
2339 uint32_t clock; local
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/freebsd-13-stable/contrib/libevent/test/
H A Dtest-changelist.c75 timer->ticksBegin = clock();
125 ticksEnd = clock();
/freebsd-13-stable/contrib/ntp/sntp/libevent/test/
H A Dtest-changelist.c75 timer->ticksBegin = clock();
125 ticksEnd = clock();
/freebsd-13-stable/sys/dev/sdhci/
H A Dfsl_sdhci.c163 * The clock enable bits exist in different registers for ESDHC vs USDHC, but
165 * standard sdhci clock register, but in different bit positions and meanings
325 * The hardware leaves the base clock frequency out of the capabilities
328 * in an sdhci 2.0 capabliities register. The timeout clock is the same
428 * The clock control stuff is complex enough to have its own function
528 * Whenever the sdhci driver writes the clock register we save a
532 * those bits, and mix in the clock status and enable bits that come
538 * The internal clock is always enabled (actually, the hardware manages
539 * it). Whether the internal clock is stable yet after a frequency
547 * On i.MX ESDHC hardware the card bus clock enabl
775 uint32_t clock; local
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/freebsd-13-stable/sys/contrib/octeon-sdk/
H A Dcvmx-hfa.c57 #include <asm/octeon/cvmx-clock.h>
H A Dcvmx-uart.c44 #include <asm/octeon/cvmx-clock.h>
87 * CPU clock frequency in Hz
/freebsd-13-stable/sys/dev/mmc/
H A Dmmcbrvar.h93 MMCBR_ACCESSOR(clock, CLOCK, int)
/freebsd-13-stable/sys/dev/bhnd/cores/chipc/pwrctl/
H A Dbhnd_pwrctlvar.h62 * Early ChipCommon revisions do not support dynamic clock control
68 * (rev <= 5) vend xtal/pll and clock config registers via the PCI
71 * Dynamic clock control is not supported on these devices.
77 * clock is available, and the HT clock must be enabled.
94 * device clock reservation.
98 bhnd_clock clock; /**< requested clock */ member in struct:bhnd_pwrctl_clkres
114 /** active clock reservations */
/freebsd-13-stable/sys/mips/cavium/
H A Docteon_rnd.c37 #include <sys/clock.h>
H A Docteon_rtc.c37 #include <sys/clock.h>
58 /* clock interface */
/freebsd-13-stable/sys/dev/tws/
H A Dtws_services.h129 #include <sys/clock.h>
/freebsd-13-stable/sys/dev/smartpqi/
H A Dsmartpqi_includes.h57 #include <sys/clock.h>
/freebsd-13-stable/sys/arm/arm/
H A Dmpcore_timer.c342 * and max period values to some value calculated from the clock
343 * frequency. We might not know yet what our runtime clock frequency
345 * that even if our base clock frequency is 2GHz (meaning a 4GHz CPU),
379 pcell_t clock; local
391 /* Get the base clock frequency */
393 if ((OF_getencprop(node, "clock-frequency", &clock,
394 sizeof(clock))) <= 0) {
395 device_printf(dev, "missing clock-frequency "
399 sc->clkfreq = clock;
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/freebsd-13-stable/sys/arm/nvidia/
H A Das3722_rtc.c33 #include <sys/clock.h>
/freebsd-13-stable/sys/arm/versatile/
H A Dsp804.c209 pcell_t clock; local
228 /* Get the base clock frequency */
230 if ((OF_getencprop(node, "clock-frequency", &clock, sizeof(clock))) > 0) {
231 sc->sysclk_freq = clock;
240 device_printf(dev, "Unable to setup the clock irq handler.\n");

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