/freebsd-13-stable/contrib/unbound/sldns/ |
H A D | parseutil.c | 147 sldns_gmtime64_r(int64_t clock, struct tm *result) argument 150 result->tm_sec = (int) LDNS_MOD(clock, 60); 151 clock = LDNS_DIV(clock, 60); 152 result->tm_min = (int) LDNS_MOD(clock, 60); 153 clock = LDNS_DIV(clock, 60); 154 result->tm_hour = (int) LDNS_MOD(clock, 24); 155 clock = LDNS_DIV(clock, 2 [all...] |
/freebsd-13-stable/contrib/ldns/ |
H A D | util.c | 275 ldns_gmtime64_r(int64_t clock, struct tm *result) argument 278 result->tm_sec = (int) LDNS_MOD(clock, 60); 279 clock = LDNS_DIV(clock, 60); 280 result->tm_min = (int) LDNS_MOD(clock, 60); 281 clock = LDNS_DIV(clock, 60); 282 result->tm_hour = (int) LDNS_MOD(clock, 24); 283 clock = LDNS_DIV(clock, 2 [all...] |
/freebsd-13-stable/sys/dev/drm2/ |
H A D | drm_modes.c | 53 mode->base.id, mode->name, mode->vrefresh, mode->clock, 259 /* 15/13. Find pixel clock frequency (kHz for xf86) */ 260 drm_mode->clock = drm_mode->htotal * HV_FACTOR * 1000 / hperiod; 261 drm_mode->clock -= drm_mode->clock % CVT_CLOCK_STEP; 425 /* 21.Find pixel clock frequency: */ 450 drm_mode->clock = pixel_freq; 606 calc_val = (mode->clock * 1000) / mode->htotal; /* hsync in Hz */ 641 calc_val = (mode->clock * 1000); 773 /* do clock chec [all...] |
/freebsd-13-stable/contrib/sendmail/libsm/ |
H A D | fpos.c | 22 #include <sm/clock.h>
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H A D | t-event.c | 22 #include <sm/clock.h>
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H A D | fclose.c | 26 #include <sm/clock.h>
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/freebsd-13-stable/sys/dev/twa/ |
H A D | tw_osl_share.h | 51 #include <sys/clock.h>
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/freebsd-13-stable/sys/x86/x86/ |
H A D | delay.c | 35 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 50 #include <machine/clock.h>
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/freebsd-13-stable/contrib/llvm-project/compiler-rt/lib/tsan/rtl/ |
H A D | tsan_clock.cpp | 18 // ThreadClock contains fixed-size vector clock for maximum number of threads. 19 // SyncClock contains growable vector clock for currently necessary number of 25 // clock[i] = max(clock[i], src->clock[i]); 30 // dst->clock[i] = max(dst->clock[i], clock[i]); 35 // tmp = clock[i]; 36 // clock[ [all...] |
/freebsd-13-stable/sys/mips/mediatek/ |
H A D | mtk_spi_v1.c | 251 uint32_t cs, clock, mode; local 258 spibus_get_clock(child, &clock); 286 if (clock != 0) { 287 div = (mtk_soc_get_cpuclk() + (clock - 1)) / clock;
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/freebsd-13-stable/sys/dev/bhnd/cores/pmu/ |
H A D | bhnd_pmu_subr.c | 348 /* d11 slow to fast clock transition time in slow clock cycles */ 1146 /* setup pll and query clock speed */ 1176 /* setup pll and query clock speed */ 1451 /* query alp/xtal clock frequency */ 1550 /* Wait for HT clock to shutdown. */ 1599 /* query alp/xtal clock frequency */ 1620 /* query CPU clock frequency */ 1664 /* Return ARM/SB clock */ 1735 /* Wait for HT clock t 2150 uint32_t clock; local 2289 uint32_t chipst, clock; local 2339 uint32_t clock; local [all...] |
/freebsd-13-stable/contrib/libevent/test/ |
H A D | test-changelist.c | 75 timer->ticksBegin = clock(); 125 ticksEnd = clock();
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/freebsd-13-stable/contrib/ntp/sntp/libevent/test/ |
H A D | test-changelist.c | 75 timer->ticksBegin = clock(); 125 ticksEnd = clock();
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/freebsd-13-stable/sys/dev/sdhci/ |
H A D | fsl_sdhci.c | 163 * The clock enable bits exist in different registers for ESDHC vs USDHC, but 165 * standard sdhci clock register, but in different bit positions and meanings 325 * The hardware leaves the base clock frequency out of the capabilities 328 * in an sdhci 2.0 capabliities register. The timeout clock is the same 428 * The clock control stuff is complex enough to have its own function 528 * Whenever the sdhci driver writes the clock register we save a 532 * those bits, and mix in the clock status and enable bits that come 538 * The internal clock is always enabled (actually, the hardware manages 539 * it). Whether the internal clock is stable yet after a frequency 547 * On i.MX ESDHC hardware the card bus clock enabl 775 uint32_t clock; local [all...] |
/freebsd-13-stable/sys/contrib/octeon-sdk/ |
H A D | cvmx-hfa.c | 57 #include <asm/octeon/cvmx-clock.h>
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H A D | cvmx-uart.c | 44 #include <asm/octeon/cvmx-clock.h> 87 * CPU clock frequency in Hz
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/freebsd-13-stable/sys/dev/mmc/ |
H A D | mmcbrvar.h | 93 MMCBR_ACCESSOR(clock, CLOCK, int)
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/freebsd-13-stable/sys/dev/bhnd/cores/chipc/pwrctl/ |
H A D | bhnd_pwrctlvar.h | 62 * Early ChipCommon revisions do not support dynamic clock control 68 * (rev <= 5) vend xtal/pll and clock config registers via the PCI 71 * Dynamic clock control is not supported on these devices. 77 * clock is available, and the HT clock must be enabled. 94 * device clock reservation. 98 bhnd_clock clock; /**< requested clock */ member in struct:bhnd_pwrctl_clkres 114 /** active clock reservations */
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/freebsd-13-stable/sys/mips/cavium/ |
H A D | octeon_rnd.c | 37 #include <sys/clock.h>
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H A D | octeon_rtc.c | 37 #include <sys/clock.h> 58 /* clock interface */
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/freebsd-13-stable/sys/dev/tws/ |
H A D | tws_services.h | 129 #include <sys/clock.h>
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/freebsd-13-stable/sys/dev/smartpqi/ |
H A D | smartpqi_includes.h | 57 #include <sys/clock.h>
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/freebsd-13-stable/sys/arm/arm/ |
H A D | mpcore_timer.c | 342 * and max period values to some value calculated from the clock 343 * frequency. We might not know yet what our runtime clock frequency 345 * that even if our base clock frequency is 2GHz (meaning a 4GHz CPU), 379 pcell_t clock; local 391 /* Get the base clock frequency */ 393 if ((OF_getencprop(node, "clock-frequency", &clock, 394 sizeof(clock))) <= 0) { 395 device_printf(dev, "missing clock-frequency " 399 sc->clkfreq = clock; [all...] |
/freebsd-13-stable/sys/arm/nvidia/ |
H A D | as3722_rtc.c | 33 #include <sys/clock.h>
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/freebsd-13-stable/sys/arm/versatile/ |
H A D | sp804.c | 209 pcell_t clock; local 228 /* Get the base clock frequency */ 230 if ((OF_getencprop(node, "clock-frequency", &clock, sizeof(clock))) > 0) { 231 sc->sysclk_freq = clock; 240 device_printf(dev, "Unable to setup the clock irq handler.\n");
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