Lines Matching refs:clock
163 * The clock enable bits exist in different registers for ESDHC vs USDHC, but
165 * standard sdhci clock register, but in different bit positions and meanings
325 * The hardware leaves the base clock frequency out of the capabilities
328 * in an sdhci 2.0 capabliities register. The timeout clock is the same
428 * The clock control stuff is complex enough to have its own function
528 * Whenever the sdhci driver writes the clock register we save a
532 * those bits, and mix in the clock status and enable bits that come
538 * The internal clock is always enabled (actually, the hardware manages
539 * it). Whether the internal clock is stable yet after a frequency
547 * On i.MX ESDHC hardware the card bus clock enable is in the usual
551 * no force-off for the card bus clock (the hardware runs the clock when
552 * transfers are active no matter what), so we always say the clock is
585 * start and stop the sd bus clock. If the enable bit is not
586 * set, turn off the clock in hardware and we're done, otherwise
603 * over the sd bus clock, but no way to turn it off. (If a cmd
604 * or data transfer is in progress the clock is on, otherwise it
605 * is off.) If the clock is being disabled, we can just return
775 uint32_t clock;
780 if((OF_getprop(node, "clock-frequency", (void *)&clock,
781 sizeof(clock)) <= 0) || (clock == 0)) {
782 clock = mpc85xx_get_system_clock();
784 if (clock == 0) {
793 device_printf(dev, "Acquired clock: %d from DTS\n", clock);
795 return (clock);