Searched refs:clock (Results 301 - 325 of 371) sorted by relevance

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/freebsd-13-stable/contrib/sendmail/libsm/
H A Dldap.c24 # include <sm/clock.h>
/freebsd-13-stable/contrib/llvm-project/compiler-rt/lib/tsan/rtl/
H A Dtsan_rtl.h401 ThreadClock clock; member in struct:__tsan::ThreadState
/freebsd-13-stable/sys/contrib/octeon-sdk/
H A Dcvmx-usbd.c55 #include <asm/octeon/cvmx-clock.h>
65 #include "cvmx-clock.h"
252 /* Try to determine clock type automatically */
264 /* Check for auto ref clock frequency */
292 /* 2b. Select the USB reference clock/crystal parameters by writing
296 /* The USB port uses 12/24/48MHz 2.5V board clock
324 /* The USB port uses a 12MHz crystal as clock source
339 setting USBN0/1_CLK_CTL[ENABLE] = 1. Divide the core clock down such
352 /* 2e. Wait 64 core-clock cycles for HCLK to stabilize */
354 /* 3. Program the power-on reset field in the USBN clock
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H A Dcvmx-helper.c75 #include <asm/octeon/cvmx-clock.h>
/freebsd-13-stable/sys/dev/drm2/
H A Ddrm_irq.c465 /* Dot clock in Hz: */
466 dotclock = (u64) crtc->hwmode.clock * 1000;
476 /* Convert scanline length in pixels and video dot clock to
495 DRM_DEBUG("crtc %d: clock %d kHz framedur %d linedur %d, pixeldur %d\n",
/freebsd-13-stable/sys/dev/hwpmc/
H A Dhwpmc_logging.c66 #include <machine/clock.h>
/freebsd-13-stable/sys/dev/atkbdc/
H A Datkbdc.c50 #include <machine/clock.h>
/freebsd-13-stable/sys/i386/i386/
H A Dtrap.c105 #include <machine/clock.h>
/freebsd-13-stable/sys/kern/
H A Dkern_clocksource.c55 #include <machine/clock.h>
718 * Switch to profiling clock rates.
738 * Switch to regular clock rates.
/freebsd-13-stable/sys/mips/ingenic/
H A Djz4780_clock.c58 #include <dt-bindings/clock/jz4780-cgu.h>
61 * JZ4780 CGU clock domain
146 /* OTG PHY clock (reuse gate def structure */
405 /* Register OTG clock */
479 "unable to reparent uhc clock\n");
483 device_printf(sc->dev, "unable to init uhc clock\n");
485 device_printf(sc->dev, "unable to lookup uhc clock\n");
709 * clock anyway. Follow their lead blindly.
716 /* Enable OTG, should not be necessary since we use PLL clock */
/freebsd-13-stable/sys/powerpc/powermac/
H A Dpmu.c44 #include <sys/clock.h>
/freebsd-13-stable/sys/amd64/vmm/io/
H A Dvrtc.c41 #include <sys/clock.h>
/freebsd-13-stable/sys/arm/allwinner/clkng/
H A Dccu_a31.c52 #include <dt-bindings/clock/sun6i-a31-ccu.h>
/freebsd-13-stable/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_per.c41 #include <dt-bindings/clock/tegra124-car.h>
374 /* Peripheral clock clock */
392 /* Basic pheripheral clock */
722 ("Invalid clock index for enable: %d", idx));
730 ("Invalid clock index for reset: %d", idx));
H A Dtegra124_clk_pll.c41 #include <dt-bindings/clock/tegra124-car.h>
127 PLLM: Clock source for EMC 2x clock
134 PLLA: Audio clock sources: (11.2896 MHz, 12.288 MHz, 24.576 MHz)
139 PLLE: generate the 100 MHz reference clock for USB 3.0 (spread spectrum)
142 DFLLCPU: DFLL clock source for the fast CPU cluster
219 /* PLLM: 880 MHz Clock source for EMC 2x clock */
301 /* PLLA: Audio clock sources: (11.2896 MHz, 12.288 MHz, 24.576 MHz) */
358 /* PLLE: generate the 100 MHz reference clock for USB 3.0 (spread spectrum) */
780 * PLLD2 is used as source for pixel clock for HDMI.
849 * HDMI specification allows 5% pixel clock toleranc
[all...]
/freebsd-13-stable/sys/arm/nvidia/
H A Dtegra_xhci.c38 #include <sys/clock.h>
437 device_printf(sc->dev, "Cannot get 'xusb_host' clock\n");
443 device_printf(sc->dev, "Cannot get 'xusb_falcon_src' clock\n");
449 device_printf(sc->dev, "Cannot get 'xusb_ss' clock\n");
455 device_printf(sc->dev, "Cannot get 'xusb_hs_src' clock\n");
461 device_printf(sc->dev, "Cannot get 'xusb_fs_src' clock\n");
467 device_printf(sc->dev, "Cannot get 'xusb_gate' clock\n");
514 /* Setup XUSB ss_src clock first */
519 /* The XUSB gate clock must be enabled before XUSBA can be powered. */
523 "Cannot enable 'xusb_gate' clock\
[all...]
/freebsd-13-stable/sys/arm/ti/am335x/
H A Dam335x_lcd.c37 #include <sys/clock.h>
468 "clock-frequency", &panel->panel_pxl_clk)))
627 * try to adjust clock to get double of requested frequency
732 /* clock signal settings */
H A Dtda19988.c36 #include <sys/clock.h>
/freebsd-13-stable/sys/arm64/nvidia/tegra210/
H A Dtegra210_clk_per.c42 #include <dt-bindings/clock/tegra210-car.h>
482 /* Peripheral clock clock */
501 /* Basic pheripheral clock */
836 ("Invalid clock index for enable: %d", idx));
844 ("Invalid clock index for reset: %d", idx));
/freebsd-13-stable/sys/arm64/rockchip/
H A Drk805.c33 #include <sys/clock.h>
629 /* Register this as a 1Hz clock */
668 * If the reported year is earlier than 2019, assume the clock is unset.
/freebsd-13-stable/sys/amd64/amd64/
H A Dmp_machdep.c69 #include <machine/clock.h>
/freebsd-13-stable/sys/amd64/linux32/
H A Dlinux32_machdep.c40 #include <sys/clock.h>
/freebsd-13-stable/sys/x86/x86/
H A Dcpu_machdep.c77 #include <machine/clock.h>
268 /* Get current clock frequency for the given cpu id. */
H A Dmp_x86.c73 #include <machine/clock.h>
/freebsd-13-stable/sys/contrib/zstd/programs/
H A Dfileio.c1498 clock_t const cpuStart = clock();
1565 { clock_t const cpuEnd = clock();

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