/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InsertWait.cpp | 53 const TargetInstrInfo *TII; // Machine instruction info. member in class:__anon4444::WaitInsert 122 TII = ST.getInstrInfo(); 143 BuildMI(MBB, AfterMI, MI->getDebugLoc(), TII->get(X86::WAIT));
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H A D | X86SpeculativeExecutionSideEffectSuppression.cpp | 105 const X86InstrInfo *TII = Subtarget.getInstrInfo(); local 124 BuildMI(MBB, MI, DebugLoc(), TII->get(X86::LFENCE)); 164 BuildMI(MBB, FirstTerminator, DebugLoc(), TII->get(X86::LFENCE));
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H A D | X86FrameLowering.cpp | 48 STI(STI), TII(*STI.getInstrInfo()), TRI(STI.getRegisterInfo()) { 280 BuildMI(MBB, MBBI, DL, TII.get(X86::STACKALLOC_W_PROBING)).addImm(Offset); 297 BuildMI(MBB, MBBI, DL, TII.get(MovRIOpc), Reg) 300 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AddSubRROpc), StackPtr) 314 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r)) 323 BuildMI(MBB, MBBI, DL, TII.get(MovRIOpc), Rax) 326 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(X86::ADD64rr), Rax) 332 BuildMI(MBB, MBBI, DL, TII.get(X86::XCHG64rm), Rax).addReg(Rax), 335 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rm), StackPtr), 353 BuildMI(MBB, MBBI, DL, TII [all...] |
H A D | X86CallFrameOptimization.cpp | 119 const X86InstrInfo *TII = nullptr; member in class:__anon4414::X86CallFrameOptimization 164 unsigned FrameSetupOpcode = TII->getCallFrameSetupOpcode(); 165 unsigned FrameDestroyOpcode = TII->getCallFrameDestroyOpcode(); 172 if (TII->getFrameSize(MI) >= StackProbeSize && EmitStackProbeCall) 238 TII = STI->getInstrInfo(); 251 unsigned FrameSetupOpcode = TII->getCallFrameSetupOpcode(); 363 assert(I->getOpcode() == TII->getCallFrameSetupOpcode()); 369 unsigned int MaxAdjust = TII->getFrameSize(*FrameSetup) >> Log2SlotSize; 470 if ((++I)->getOpcode() != TII->getCallFrameDestroyOpcode()) 500 TII [all...] |
H A D | X86InstructionSelector.cpp | 134 const X86InstrInfo &TII; member in class:__anon4453::X86InstructionSelector 156 : InstructionSelector(), TM(TM), STI(STI), TII(*STI.getInstrInfo()), 256 TII.get(TargetOpcode::SUBREG_TO_REG)) 300 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) 305 I.setDesc(TII.get(X86::COPY)); 537 I.setDesc(TII.get(NewOpc)); 548 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); 573 I.setDesc(TII.get(NewOpc)); 585 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); 625 I.setDesc(TII [all...] |
H A D | X86AvoidTrailingCall.cpp | 83 const X86InstrInfo &TII = *STI.getInstrInfo(); local 129 BuildMI(MBB, MBBI, DL, TII.get(X86::INT3));
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFRegisterInfo.cpp | 82 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 90 BuildMI(MBB, ++II, DL, TII.get(BPF::ADD_ri), reg) 110 BuildMI(MBB, ++II, DL, TII.get(BPF::MOV_rr), reg) 112 BuildMI(MBB, II, DL, TII.get(BPF::ADD_ri), reg)
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonSplitConst32AndConst64.cpp | 68 const TargetInstrInfo *TII = HST.getInstrInfo(); local 82 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestReg) 95 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestLo) 97 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestHi)
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64CleanupLocalDynamicTLSPass.cpp | 100 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); local 105 TII->get(TargetOpcode::COPY), AArch64::X0) 122 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); local 131 TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
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H A D | AArch64SIMDInstrOpt.cpp | 69 const TargetInstrInfo *TII; member in struct:__anon3866::AArch64SIMDInstrOpt 282 OriginalMCID = &TII->get(AArch64::FMLAv4i32_indexed); 283 ReplInstrMCID.push_back(&TII->get(AArch64::DUPv4i32lane)); 284 ReplInstrMCID.push_back(&TII->get(AArch64::FMLAv4f32)); 297 OriginalMCID = &TII->get(I.OrigOpc); 299 ReplInstrMCID.push_back(&TII->get(Repl)); 361 DupMCID = &TII->get(AArch64::DUPv4i32lane); 362 MulMCID = &TII->get(AArch64::FMLAv4f32); 365 DupMCID = &TII->get(AArch64::DUPv4i32lane); 366 MulMCID = &TII [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | ExpandPostRAPseudos.cpp | 34 const TargetInstrInfo *TII; member in struct:__anon3460::ExpandPostRA 99 MI->setDesc(TII->get(TargetOpcode::KILL)); 112 MI->setDesc(TII->get(TargetOpcode::KILL)); 120 TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg, 139 MI->setDesc(TII->get(TargetOpcode::KILL)); 156 MI->setDesc(TII->get(TargetOpcode::KILL)); 166 TII->copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(), 187 TII = MF.getSubtarget().getInstrInfo(); 204 if (TII->expandPostRAPseudo(MI)) {
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H A D | BranchFolding.cpp | 192 TII = tii; 384 BuildMI(OldMBB, OldInst, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Reg); 388 TII->ReplaceTailWithBranchTo(OldInst, &NewDest); 395 if (!TII->isLegalToSplitMBBAt(CurMBB, BBI1)) 458 const TargetInstrInfo *TII) { 464 if (I != MF->end() && !TII->analyzeBranch(*CurMBB, TBB, FBB, Cond, true)) { 467 if (!TII->reverseBranchCondition(Cond)) { 468 TII->removeBranch(*CurMBB); 469 TII->insertBranch(*CurMBB, SuccBB, nullptr, Cond, dl); 474 TII 457 FixTail(MachineBasicBlock *CurMBB, MachineBasicBlock *SuccBB, const TargetInstrInfo *TII) argument 1269 copyDebugInfoToPredecessor(const TargetInstrInfo *TII, MachineBasicBlock &MBB, MachineBasicBlock &PredMBB) argument 1281 copyDebugInfoToSuccessor(const TargetInstrInfo *TII, MachineBasicBlock &MBB, MachineBasicBlock &SuccMBB) argument 1300 salvageDebugInfoFromEmptyBlock(const TargetInstrInfo *TII, MachineBasicBlock &MBB) argument 1797 findHoistingInsertPosAndDeps(MachineBasicBlock *MBB, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, SmallSet<Register, 4> &Uses, SmallSet<Register, 4> &Defs) argument [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIFixSGPRCopies.cpp | 119 const SIInstrInfo *TII; member in class:__anon3968::SIFixSGPRCopies 204 const SIInstrInfo *TII) { 219 !TII->isOperandLegal(*UseMI, UseMI->getOperandNo(&MO), &Src)) 242 const SIInstrInfo *TII, 267 if (tryChangeVGPRtoSGPRinCopy(CopyUse, TRI, TII)) 301 BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(), TII->get(AMDGPU::COPY), 310 BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(), TII->get(Opc), 325 const SIInstrInfo *TII, 335 TII->getNamedOperand(*MoveImm, AMDGPU::OpName::src0); 410 getFirstNonPrologue(MachineBasicBlock *MBB, const TargetInstrInfo *TII) { 202 tryChangeVGPRtoSGPRinCopy(MachineInstr &MI, const SIRegisterInfo *TRI, const SIInstrInfo *TII) argument 240 foldVGPRCopyIntoRegSequence(MachineInstr &MI, const SIRegisterInfo *TRI, const SIInstrInfo *TII, MachineRegisterInfo &MRI) argument 323 isSafeToFoldImmIntoCopy(const MachineInstr *Copy, const MachineInstr *MoveImm, const SIInstrInfo *TII, unsigned &SMovOp, int64_t &Imm) argument [all...] |
H A D | R600MachineScheduler.cpp | 31 TII = static_cast<const R600InstrInfo*>(DAG->TII); 38 InstKindLimit[IDAlu] = TII->getMaxAlusPerClause(); 222 if (TII->isTransOnly(*MI)) 246 if(TII->isVector(*MI) || 247 TII->isCubeOp(MI->getOpcode()) || 248 TII->isReductionOp(MI->getOpcode()) || 253 if (TII->isLDSInstr(MI->getOpcode())) { 287 if (TII->readsLDSSrcReg(*MI)) 296 if (TII [all...] |
H A D | SILowerSGPRSpills.cpp | 50 const SIInstrInfo *TII = nullptr; member in class:__anon3983::SILowerSGPRSpills 92 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); local 106 TII.storeRegToStackSlot(SaveBlock, I, Reg, true, CS.getFrameIdx(), RC, 125 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); local 140 TII.loadRegFromStackSlot(RestoreBlock, I, Reg, CI.getFrameIdx(), RC, TRI); 276 TII = ST.getInstrInfo(); 277 TRI = &TII->getRegisterInfo(); 322 if (SpillToAGPR && TII->isVGPRSpill(MI)) { 329 TII->getNamedOperand(MI, AMDGPU::OpName::vdata)->getReg(); 337 if (!TII [all...] |
H A D | SIOptimizeExecMaskingPreRA.cpp | 32 const SIInstrInfo *TII; member in class:__anon3988::SIOptimizeExecMaskingPreRA 101 const SIInstrInfo *TII = ST.getInstrInfo(); local 138 MachineOperand *Op1 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src0); 139 MachineOperand *Op2 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src1); 150 if (TII->hasModifiersSet(*Sel, AMDGPU::OpName::src0_modifiers) || 151 TII->hasModifiersSet(*Sel, AMDGPU::OpName::src1_modifiers)) 154 Op1 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src0); 155 Op2 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src1); 156 MachineOperand *CC = TII->getNamedOperand(*Sel, AMDGPU::OpName::src2); 167 BuildMI(MBB, *And, And->getDebugLoc(), TII [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSEFrameLowering.cpp | 92 const MipsSEInstrInfo &TII; member in class:__anon4228::ExpandPseudo 101 TII(*static_cast<const MipsSEInstrInfo *>(Subtarget.getInstrInfo())), 177 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0); 178 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst) 192 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR) 194 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0); 213 const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY); 215 TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0); 217 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize); 238 BuildMI(MBB, I, DL, TII 406 const MipsSEInstrInfo &TII = local 694 const MipsSEInstrInfo &TII = local 796 const TargetInstrInfo &TII = *STI.getInstrInfo(); local [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiRegisterInfo.cpp | 138 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); local 183 BuildMI(*MI.getParent(), II, DL, TII->get(Lanai::MOVHI), Reg) 185 BuildMI(*MI.getParent(), II, DL, TII->get(Lanai::OR_I_LO), Reg) 190 BuildMI(*MI.getParent(), II, DL, TII->get(Lanai::ADD_I_LO), Reg) 197 HasNegOffset ? TII->get(Lanai::SUB_R) : TII->get(Lanai::ADD_R), 206 MI.setDesc(TII->get(getRRMOpcodeVariant(MI.getOpcode()))); 233 BuildMI(*MI.getParent(), II, DL, TII->get(NewOpcode),
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | InstructionSelector.cpp | 38 const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, 44 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, RC, 36 constrainOperandRegToRegClass( MachineInstr &I, unsigned OpIdx, const TargetRegisterClass &RC, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) const argument
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCRegisterInfo.cpp | 39 const ARCInstrInfo &TII, unsigned Reg, 50 BuildMI(MBB, II, dl, TII.get(ARC::LD_rlimm), Reg) 75 BuildMI(MBB, II, dl, TII.get(AddOpc)) 93 BuildMI(MBB, II, dl, TII.get(MI.getOpcode()), Reg) 106 BuildMI(MBB, II, dl, TII.get(MI.getOpcode())) 115 TII.get(isUInt<6>(Offset) ? ARC::ADD_rru6 : ARC::ADD_rrlimm)) 169 const ARCInstrInfo &TII = *MF.getSubtarget<ARCSubtarget>().getInstrInfo(); local 217 ReplaceFrameIndex(II, TII, Reg, getFrameRegister(MF), Offset, StackSize, 38 ReplaceFrameIndex(MachineBasicBlock::iterator II, const ARCInstrInfo &TII, unsigned Reg, unsigned FrameReg, int Offset, int StackSize, int ObjSize, RegScavenger *RS, int SPAdj) argument
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVInstructionSelector.cpp | 45 const RISCVInstrInfo &TII; member in class:__anon4296::RISCVInstructionSelector 72 : InstructionSelector(), STI(STI), TII(*STI.getInstrInfo()),
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZHazardRecognizer.h | 47 const SystemZInstrInfo *TII; member in class:llvm::SystemZHazardRecognizer 112 : TII(tii), SchedModel(SM) {
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/XCore/ |
H A D | XCoreFrameToArgsOffsetElim.cpp | 48 const XCoreInstrInfo &TII = local 59 MBBI = TII.loadImmediate(MBB, MBBI, Reg, StackSize);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCRegisterInfo.cpp | 476 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); local 498 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) 502 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 506 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1) 510 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 536 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); local 559 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), FramePointer) 563 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), FramePointer) 567 BuildMI(MBB, II, dl, TII.get(PPC::LD), FramePointer) 571 BuildMI(MBB, II, dl, TII 622 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); local 666 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); local 693 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); local 738 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); local 781 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); local 890 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); local 940 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); local 966 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); local 1065 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); local [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | DelaySlotFiller.cpp | 109 const TargetInstrInfo *TII = Subtarget->getInstrInfo(); local 128 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP)); 146 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP)); 156 TII->get(SP::UNIMP)).addImm(structSize); 376 const TargetInstrInfo *TII) 391 AddMI->setDesc(TII->get((AddMI->getOpcode() == SP::ADDrr) 403 const TargetInstrInfo *TII) 430 OrMI->setDesc(TII->get((OrMI->getOpcode() == SP::ORrr) 442 const TargetInstrInfo *TII) 467 RestoreMI->setDesc(TII 374 combineRestoreADD(MachineBasicBlock::iterator RestoreMI, MachineBasicBlock::iterator AddMI, const TargetInstrInfo *TII) argument 401 combineRestoreOR(MachineBasicBlock::iterator RestoreMI, MachineBasicBlock::iterator OrMI, const TargetInstrInfo *TII) argument 440 combineRestoreSETHIi(MachineBasicBlock::iterator RestoreMI, MachineBasicBlock::iterator SetHiMI, const TargetInstrInfo *TII) argument 499 const TargetInstrInfo *TII = Subtarget->getInstrInfo(); local [all...] |