Lines Matching refs:TII
134 const X86InstrInfo &TII;
156 : InstructionSelector(), TM(TM), STI(STI), TII(*STI.getInstrInfo()),
256 TII.get(TargetOpcode::SUBREG_TO_REG))
300 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
305 I.setDesc(TII.get(X86::COPY));
537 I.setDesc(TII.get(NewOpc));
548 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
573 I.setDesc(TII.get(NewOpc));
585 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
625 I.setDesc(TII.get(NewOpc));
631 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
677 I.setDesc(TII.get(NewOpc));
678 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
698 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
702 I.setDesc(TII.get(X86::COPY));
723 LLVM_DEBUG(dbgs() << TII.getName(I.getOpcode())
761 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
768 I.setDesc(TII.get(X86::COPY));
815 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
831 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(ZextEntryIt->MovOp))
837 TII.get(TargetOpcode::SUBREG_TO_REG))
866 TII.get(TargetOpcode::SUBREG_TO_REG), DefReg)
873 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AndOpc), DstReg)
877 constrainSelectedInstRegOperands(AndInst, TII, TRI, RBI);
917 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
923 I.setDesc(TII.get(X86::COPY));
928 TII.get(TargetOpcode::SUBREG_TO_REG))
975 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpCmp))
980 TII.get(X86::SETCCr), I.getOperand(0).getReg()).addImm(CC);
982 constrainSelectedInstRegOperands(CmpInst, TII, TRI, RBI);
983 constrainSelectedInstRegOperands(SetInst, TII, TRI, RBI);
1035 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpCmp))
1042 TII.get(X86::SETCCr), FlagReg1).addImm(SETFOpc[0]);
1044 TII.get(X86::SETCCr), FlagReg2).addImm(SETFOpc[1]);
1046 TII.get(SETFOpc[2]), ResultReg)
1049 constrainSelectedInstRegOperands(CmpInst, TII, TRI, RBI);
1050 constrainSelectedInstRegOperands(Set1, TII, TRI, RBI);
1051 constrainSelectedInstRegOperands(Set2, TII, TRI, RBI);
1052 constrainSelectedInstRegOperands(Set3, TII, TRI, RBI);
1068 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpCmp))
1073 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SETCCr), ResultReg).addImm(CC);
1074 constrainSelectedInstRegOperands(CmpInst, TII, TRI, RBI);
1075 constrainSelectedInstRegOperands(Set, TII, TRI, RBI);
1107 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY), X86::EFLAGS)
1124 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode), DstReg)
1128 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY), CarryOutReg)
1131 if (!constrainSelectedInstRegOperands(AddInst, TII, TRI, RBI) ||
1174 I.setDesc(TII.get(X86::VEXTRACTF32x4Z256rr));
1176 I.setDesc(TII.get(X86::VEXTRACTF128rr));
1181 I.setDesc(TII.get(X86::VEXTRACTF32x4Zrr));
1183 I.setDesc(TII.get(X86::VEXTRACTF64x4Zrr));
1193 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1228 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY), DstReg)
1265 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY))
1307 I.setDesc(TII.get(X86::VINSERTF32x4Z256rr));
1309 I.setDesc(TII.get(X86::VINSERTF128rr));
1314 I.setDesc(TII.get(X86::VINSERTF32x4Zrr));
1316 I.setDesc(TII.get(X86::VINSERTF64x4Zrr));
1327 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1343 TII.get(TargetOpcode::G_EXTRACT), I.getOperand(Idx).getReg())
1382 TII.get(TargetOpcode::G_INSERT), Tmp)
1394 TII.get(TargetOpcode::COPY), DstReg)
1413 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::TEST8ri))
1416 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::JCC_1))
1419 constrainSelectedInstRegOperands(TestInst, TII, TRI, RBI);
1456 BuildMI(*I.getParent(), I, DbgLoc, TII.get(X86::MOV64ri), AddrReg)
1464 addDirectMem(BuildMI(*I.getParent(), I, DbgLoc, TII.get(Opc), DstReg),
1475 // PICBase can be allocated by TII.getGlobalBaseReg(&MF).
1482 BuildMI(*I.getParent(), I, DbgLoc, TII.get(Opc), DstReg), CPI, PICBase,
1487 constrainSelectedInstRegOperands(*LoadInst, TII, TRI, RBI);
1505 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
1512 I.setDesc(TII.get(X86::IMPLICIT_DEF));
1514 I.setDesc(TII.get(X86::PHI));
1640 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
1646 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpCopy),
1653 TII.get(OpEntry.OpSignExtend));
1656 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::MOV32r0),
1663 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy),
1667 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy),
1672 TII.get(TargetOpcode::SUBREG_TO_REG), TypeEntry.HighInReg)
1680 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpDivRem))
1695 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy), SourceSuperReg)
1699 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SHR16ri),
1706 TII.get(TargetOpcode::SUBREG_TO_REG))
1712 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::COPY),
1729 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::TRAP));