Searched refs:SUB (Results 76 - 89 of 89) sorted by relevance
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 358 setOperationAction(ISD::SUB, VT, Legal);
2217 if (N->getOpcode() == ISD::SUB &&
2949 return (Neg.getOpcode() == ISD::SUB &&
2963 Op = DAG.getNode(ISD::SUB, DL, Op.getValueType(),
3448 NewSP = DAG.getNode(ISD::SUB, DL, MVT::i64, OldSP, NeededSpace);
3526 Ops[1] = DAG.getNode(ISD::SUB, DL, VT, Ops[1], NegSum);
3910 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
3965 NegSrc2 = DAG.getNode(ISD::SUB, DL, MemVT, DAG.getConstant(0, DL, MemVT),
4026 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAG.cpp | 2314 case ISD::SUB:
3196 case ISD::SUB:
3861 case ISD::SUB:
3881 // Otherwise, we treat this like a SUB.
4847 case ISD::SUB: return C1 - C2;
4898 case ISD::SUB: Offset = -uint64_t(Offset); break;
5290 case ISD::SUB:
5604 case ISD::SUB:
5627 case ISD::SUB:
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| H A D | LegalizeVectorTypes.cpp | 140 case ISD::SUB:
910 case ISD::SUB:
2765 case ISD::SUB:
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| H A D | FastISel.cpp | 1853 return selectBinaryOp(I, ISD::SUB);
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| H A D | LegalizeFloatTypes.cpp | 340 Mask = DAG.getNode(ISD::SUB, dl, LVT, Mask, DAG.getConstant(1, dl, LVT));
2599 Mask = DAG.getNode(ISD::SUB, dl, LVT, Mask, DAG.getConstant(1, dl, LVT));
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1753 case ISD::SUB:
2848 return SelectBinaryIntOp(I, ISD::SUB);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAG.cpp | 599 if (Shl_0.getOpcode() == ISD::SUB) {
952 case ISD::SUB:
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 695 setOperationAction(ISD::SUB, MVT::v2i16, Legal);
724 setOperationAction(ISD::SUB, MVT::v4i16, Custom);
801 setTargetDAGCombine(ISD::SUB);
3141 ISD::ADD : ISD::SUB;
4450 case ISD::SUB:
10164 (LHSOpc == ISD::SUB && Opc == ISD::SUBCARRY)) {
10516 case ISD::SUB:
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| /freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 2422 case ISD::SUB:
4396 /// Method for building the DAG expansion of ISD::[US][ADD|SUB]SAT. This
4412 /// Method for building the DAG expansion of ISD::U(ADD|SUB)O. Expansion
4417 /// Method for building the DAG expansion of ISD::S(ADD|SUB)O. Expansion
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1650 case Sub: return ISD::SUB;
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 505 setTargetDAGCombine(ISD::SUB);
1178 case ISD::SUB:
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 1126 // ADD/SUB. Instead it will use [BaseReg + 0] address mode and generate
1132 // ADD/SUB:
1139 // Also skip the immediate can be encoded by a single ADD (SUB is also
2773 if (ShiftAmt->getOpcode() == ISD::ADD || ShiftAmt->getOpcode() == ISD::SUB) {
2779 // to avoid the ADD/SUB.
2783 // generate a NEG instead of a SUB of a constant.
2784 else if (ShiftAmt->getOpcode() == ISD::SUB &&
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 4199 SubOp = Mips::SUB;
5149 TOut.emitRRR(Mips::SUB, FirstRegOp, Mips::ZERO, SecondRegOp, IDLoc, STI);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 2601 SDValue NewSP = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
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Completed in 505 milliseconds
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