Searched refs:MUL (Results 51 - 75 of 79) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp122 setOperationAction(ISD::MUL, MVT::i8, Promote);
127 setOperationAction(ISD::MUL, MVT::i16, LibCall);
/freebsd-13-stable/contrib/bearssl/src/
H A Dinner.h931 #define MUL(x, y) ((uint64_t)(x) * (uint64_t)(y)) macro
/freebsd-13-stable/contrib/byacc/test/btyacc/
H A Dquote_calc.tab.c174 #define MUL 262 macro
338 0,0,"error","OP_ADD","\"ADD\"","OP_SUB","\"SUB\"","OP_MUL","\"MUL\"","OP_DIV",
H A Dquote_calc2.tab.c174 #define MUL 262 macro
338 0,0,"error","OP_ADD","\"ADD\"","OP_SUB","\"SUB\"","OP_MUL","\"MUL\"","OP_DIV",
352 "expr : expr \"MUL\" expr",
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp301 MachineInstr *Mul = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MUL))
H A DMipsISelLowering.cpp968 if (ROOTNode->getOperand(0).getOpcode() != ISD::MUL &&
969 ROOTNode->getOperand(1).getOpcode() != ISD::MUL)
998 SDValue Mult = ROOTNode->getOperand(0).getOpcode() == ISD::MUL
1002 SDValue AddOperand = ROOTNode->getOperand(0).getOpcode() == ISD::MUL
H A DMipsFastISel.cpp2127 // We treat the MUL instruction in a special way because it clobbers
2133 if (MachineInstOpcode == Mips::MUL) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp606 case ISD::MUL:
H A DAArch64ISelLowering.cpp712 setTargetDAGCombine(ISD::MUL);
796 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
832 // AArch64 doesn't have MUL.2d:
833 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
835 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
836 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
837 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
2446 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
2488 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
3079 "unexpected type for custom-lowering ISD::MUL");
[all...]
H A DAArch64ISelDAGToDAG.cpp639 if (Op1.getOpcode() != ISD::MUL ||
643 if (Op1.getOpcode() != ISD::MUL ||
/freebsd-13-stable/contrib/llvm-project/llvm/lib/TableGen/
H A DRecord.cpp1014 case MUL:
1030 case MUL: Result = LHSv * RHSv; break;
1060 case MUL: Result = "!mul"; break;
H A DTGParser.cpp1091 case tgtok::XMUL: Code = BinOpInit::MUL; break;
1240 Code != BinOpInit::MUL)
1277 Code == BinOpInit::MUL) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp127 setOperationAction(ISD::MUL, XLenVT, Expand);
137 setOperationAction(ISD::MUL, MVT::i32, Custom);
978 case ISD::MUL:
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp695 setOperationAction(ISD::MUL , VT, Expand);
799 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
808 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
810 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
812 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
813 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
870 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
1273 setTargetDAGCombine(ISD::MUL);
3305 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
11189 case ISD::MUL
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp365 case ISD::MUL:
H A DLegalizeVectorTypes.cpp136 case ISD::MUL:
911 case ISD::MUL:
2121 case ISD::VECREDUCE_MUL: CombineOpc = ISD::MUL; break;
2761 case ISD::MUL:
H A DSelectionDAG.cpp2830 case ISD::MUL: {
3889 case ISD::MUL: {
4848 case ISD::MUL: return C1 * C2;
5299 case ISD::MUL:
5633 case ISD::MUL:
5886 Value = DAG.getNode(ISD::MUL, dl, IntVT, Value,
H A DSelectionDAGBuilder.cpp3853 IdxN = DAG.getNode(ISD::MUL, dl, N.getValueType(), IdxN, VScale);
3866 IdxN = DAG.getNode(ISD::MUL, dl,
3902 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp883 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
885 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
886 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
887 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
1104 setOperationAction(ISD::MUL, MVT::i64, Expand);
1501 setTargetDAGCombine(ISD::MUL);
5586 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, dl, PTy));
8878 "unexpected type for custom-lowering ISD::MUL");
9531 case ISD::VECREDUCE_MUL: BaseOpcode = ISD::MUL; break;
9771 case ISD::MUL
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/TableGen/
H A DRecord.h807 enum BinaryOp : uint8_t { ADD, MUL, AND, OR, SHL, SRA, SRL, LISTCONCAT,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp696 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
725 setOperationAction(ISD::MUL, MVT::v4i16, Custom);
4451 case ISD::MUL:
5043 SDValue Result = DAG.getNode(ISD::MUL, SL, VT, LHS, RHS);
10032 if ((LHS.getOpcode() == ISD::MUL || RHS.getOpcode() == ISD::MUL)
10036 if (LHS.getOpcode() != ISD::MUL)
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h2388 case ISD::MUL:
4262 /// Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes,
4266 /// \param LL Low bits of the LHS of the MUL. You can use this parameter
4268 /// \param LH High bits of the LHS of the MUL. See LL for meaning.
4269 /// \param RL Low bits of the RHS of the MUL. See LL for meaning
4270 /// \param RH High bits of the RHS of the MUL. See LL for meaning.
4278 /// Expand a MUL into two nodes. One that computes the high bits of
4281 /// \param LL Low bits of the LHS of the MUL. You can use this parameter
4283 /// \param LH High bits of the LHS of the MUL. See LL for meaning.
4284 /// \param RL Low bits of the RHS of the MUL
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1652 case Mul: return ISD::MUL;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp157 setOperationAction(ISD::MUL, MVT::v16i8, Expand);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1657 setOperationAction(ISD::MUL, MVT::i32, Expand);

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