/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 122 setOperationAction(ISD::MUL, MVT::i8, Promote); 127 setOperationAction(ISD::MUL, MVT::i16, LibCall);
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/freebsd-13-stable/contrib/bearssl/src/ |
H A D | inner.h | 931 #define MUL(x, y) ((uint64_t)(x) * (uint64_t)(y)) macro
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/freebsd-13-stable/contrib/byacc/test/btyacc/ |
H A D | quote_calc.tab.c | 174 #define MUL 262 macro 338 0,0,"error","OP_ADD","\"ADD\"","OP_SUB","\"SUB\"","OP_MUL","\"MUL\"","OP_DIV",
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H A D | quote_calc2.tab.c | 174 #define MUL 262 macro 338 0,0,"error","OP_ADD","\"ADD\"","OP_SUB","\"SUB\"","OP_MUL","\"MUL\"","OP_DIV", 352 "expr : expr \"MUL\" expr",
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsInstructionSelector.cpp | 301 MachineInstr *Mul = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MUL))
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H A D | MipsISelLowering.cpp | 968 if (ROOTNode->getOperand(0).getOpcode() != ISD::MUL && 969 ROOTNode->getOperand(1).getOpcode() != ISD::MUL) 998 SDValue Mult = ROOTNode->getOperand(0).getOpcode() == ISD::MUL 1002 SDValue AddOperand = ROOTNode->getOperand(0).getOpcode() == ISD::MUL
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H A D | MipsFastISel.cpp | 2127 // We treat the MUL instruction in a special way because it clobbers 2133 if (MachineInstOpcode == Mips::MUL) {
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64TargetTransformInfo.cpp | 606 case ISD::MUL:
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H A D | AArch64ISelLowering.cpp | 712 setTargetDAGCombine(ISD::MUL); 796 setOperationAction(ISD::MUL, MVT::v1i64, Expand); 832 // AArch64 doesn't have MUL.2d: 833 setOperationAction(ISD::MUL, MVT::v2i64, Expand); 835 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 836 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 837 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 2446 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS); 2488 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS); 3079 "unexpected type for custom-lowering ISD::MUL"); [all...] |
H A D | AArch64ISelDAGToDAG.cpp | 639 if (Op1.getOpcode() != ISD::MUL || 643 if (Op1.getOpcode() != ISD::MUL ||
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/TableGen/ |
H A D | Record.cpp | 1014 case MUL: 1030 case MUL: Result = LHSv * RHSv; break; 1060 case MUL: Result = "!mul"; break;
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H A D | TGParser.cpp | 1091 case tgtok::XMUL: Code = BinOpInit::MUL; break; 1240 Code != BinOpInit::MUL) 1277 Code == BinOpInit::MUL) {
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 127 setOperationAction(ISD::MUL, XLenVT, Expand); 137 setOperationAction(ISD::MUL, MVT::i32, Custom); 978 case ISD::MUL:
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 695 setOperationAction(ISD::MUL , VT, Expand); 799 setOperationAction(ISD::MUL, MVT::v4f32, Legal); 808 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 810 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 812 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 813 setOperationAction(ISD::MUL, MVT::v16i8, Custom); 870 setOperationAction(ISD::MUL, MVT::v2f64, Legal); 1273 setTargetDAGCombine(ISD::MUL); 3305 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32, 11189 case ISD::MUL [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorOps.cpp | 365 case ISD::MUL:
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H A D | LegalizeVectorTypes.cpp | 136 case ISD::MUL: 911 case ISD::MUL: 2121 case ISD::VECREDUCE_MUL: CombineOpc = ISD::MUL; break; 2761 case ISD::MUL:
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H A D | SelectionDAG.cpp | 2830 case ISD::MUL: { 3889 case ISD::MUL: { 4848 case ISD::MUL: return C1 * C2; 5299 case ISD::MUL: 5633 case ISD::MUL: 5886 Value = DAG.getNode(ISD::MUL, dl, IntVT, Value,
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H A D | SelectionDAGBuilder.cpp | 3853 IdxN = DAG.getNode(ISD::MUL, dl, N.getValueType(), IdxN, VScale); 3866 IdxN = DAG.getNode(ISD::MUL, dl, 3902 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 883 setOperationAction(ISD::MUL, MVT::v1i64, Expand); 885 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 886 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 887 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 1104 setOperationAction(ISD::MUL, MVT::i64, Expand); 1501 setTargetDAGCombine(ISD::MUL); 5586 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, dl, PTy)); 8878 "unexpected type for custom-lowering ISD::MUL"); 9531 case ISD::VECREDUCE_MUL: BaseOpcode = ISD::MUL; break; 9771 case ISD::MUL [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/TableGen/ |
H A D | Record.h | 807 enum BinaryOp : uint8_t { ADD, MUL, AND, OR, SHL, SRA, SRL, LISTCONCAT,
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIISelLowering.cpp | 696 setOperationAction(ISD::MUL, MVT::v2i16, Legal); 725 setOperationAction(ISD::MUL, MVT::v4i16, Custom); 4451 case ISD::MUL: 5043 SDValue Result = DAG.getNode(ISD::MUL, SL, VT, LHS, RHS); 10032 if ((LHS.getOpcode() == ISD::MUL || RHS.getOpcode() == ISD::MUL) 10036 if (LHS.getOpcode() != ISD::MUL)
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | TargetLowering.h | 2388 case ISD::MUL: 4262 /// Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes, 4266 /// \param LL Low bits of the LHS of the MUL. You can use this parameter 4268 /// \param LH High bits of the LHS of the MUL. See LL for meaning. 4269 /// \param RL Low bits of the RHS of the MUL. See LL for meaning 4270 /// \param RH High bits of the RHS of the MUL. See LL for meaning. 4278 /// Expand a MUL into two nodes. One that computes the high bits of 4281 /// \param LL Low bits of the LHS of the MUL. You can use this parameter 4283 /// \param LH High bits of the LHS of the MUL. See LL for meaning. 4284 /// \param RL Low bits of the RHS of the MUL [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | TargetLoweringBase.cpp | 1652 case Mul: return ISD::MUL;
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.cpp | 157 setOperationAction(ISD::MUL, MVT::v16i8, Expand);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1657 setOperationAction(ISD::MUL, MVT::i32, Expand);
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