Searched refs:MCOperand (Results 76 - 100 of 151) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp305 ITInst.addOperand(MCOperand::createImm(ITState.Cond));
306 ITInst.addOperand(MCOperand::createImm(ITState.Mask));
414 // MCOperand, with a 1 implying 'e', regardless of the low bit of
2391 Inst.addOperand(MCOperand::createImm(0));
2393 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2395 Inst.addOperand(MCOperand::createExpr(Expr));
2410 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
2412 Inst.addOperand(MCOperand::createReg(RegNum));
2417 Inst.addOperand(MCOperand::createImm(unsigned(getVPTPred())));
2419 Inst.addOperand(MCOperand
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp239 const MCOperand &MO = MI.getOperand(OpNo);
261 const MCOperand &MO = MI.getOperand(OpNo);
283 const MCOperand &MO = MI.getOperand(OpNo);
306 const MCOperand &MO = MI.getOperand(OpNo);
329 const MCOperand &MO = MI.getOperand(OpNo);
350 const MCOperand &MO = MI.getOperand(OpNo);
371 const MCOperand &MO = MI.getOperand(OpNo);
393 const MCOperand &MO = MI.getOperand(OpNo);
415 const MCOperand &MO = MI.getOperand(OpNo);
437 const MCOperand
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H A DMipsInstPrinter.cpp127 const MCOperand &Op = MI->getOperand(OpNo);
144 const MCOperand &MO = MI->getOperand(opNum);
195 const MCOperand& MO = MI->getOperand(opNum);
H A DMipsNaClELFStreamer.cpp105 MaskInst.addOperand(MCOperand::createReg(AddrReg));
106 MaskInst.addOperand(MCOperand::createReg(AddrReg));
107 MaskInst.addOperand(MCOperand::createReg(MaskReg));
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/
H A DX86Operand.h512 Inst.addOperand(MCOperand::createImm(CE->getValue()));
514 Inst.addOperand(MCOperand::createExpr(Expr));
519 Inst.addOperand(MCOperand::createReg(getReg()));
527 Inst.addOperand(MCOperand::createReg(RegNo));
536 Inst.addOperand(MCOperand::createReg(RegNo));
570 Inst.addOperand(MCOperand::createReg(Reg));
576 Inst.addOperand(MCOperand::createReg(getMemBaseReg()));
578 Inst.addOperand(MCOperand::createReg(getMemDefaultBaseReg()));
579 Inst.addOperand(MCOperand::createImm(getMemScale()));
580 Inst.addOperand(MCOperand
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRInstPrinter.cpp121 const MCOperand &Op = MI->getOperand(OpNo);
155 const MCOperand &Op = MI->getOperand(OpNo);
177 const MCOperand &OffsetOp = MI->getOperand(OpNo + 1);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/Disassembler/
H A DWebAssemblyDisassembler.cpp105 MI.addOperand(MCOperand::createImm(Val));
117 MI.addOperand(MCOperand::createFPImm(static_cast<double>(Val)));
119 MI.addOperand(MCOperand::createImm(static_cast<int64_t>(Val)));
228 MCOperand::createImm(int64_t(WebAssembly::BlockType::Invalid)));
230 MI.addOperand(MCOperand::createImm(Val & 0x7f));
239 MI.addOperand(MCOperand::createExpr(Expr));
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonInstPrinter.cpp67 MCOperand const &MO = MI->getOperand(OpNo);
83 MCOperand const &MO = MI->getOperand(OpNo);
H A DHexagonMCInstrInfo.cpp84 MI.addOperand(MCOperand::createExpr(MCConstantExpr::create(Value, Context)));
91 MCOperand const &exOp =
99 MCB.addOperand(MCOperand::createInst(XMCI));
186 MCOperand const &MO) {
193 XMI.addOperand(MCOperand::createImm(MO.getImm() & (~0x3f)));
195 XMI.addOperand(MCOperand::createExpr(MO.getExpr()));
210 duplexInst->addOperand(MCOperand::createInst(SubInst0));
211 duplexInst->addOperand(MCOperand::createInst(SubInst1));
315 MCOperand const &
319 MCOperand cons
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H A DHexagonMCShuffler.cpp81 MCB.addOperand(MCOperand::createImm(BundleFlags));
89 MCB.addOperand(MCOperand::createInst(Extender));
90 MCB.addOperand(MCOperand::createInst(&MI));
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInstPrinter.h19 class MCOperand;
170 bool (*ValidateMCOperand)(const MCOperand &MCOp, const MCSubtargetInfo &STI,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUAsmPrinter.h36 class MCOperand;
111 bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZInstPrinter.h21 class MCOperand;
38 static void printOperand(const MCOperand &MO, const MCAsmInfo *MAI,
H A DSystemZInstPrinter.cpp42 void SystemZInstPrinter::printOperand(const MCOperand &MO, const MCAsmInfo *MAI,
150 const MCOperand &MO = MI->getOperand(OpNum);
166 const MCOperand &MO = MI->getOperand(OpNum + 1);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/VE/Disassembler/
H A DVEDisassembler.cpp114 Inst.addOperand(MCOperand::createReg(Reg));
124 Inst.addOperand(MCOperand::createReg(Reg));
134 Inst.addOperand(MCOperand::createReg(Reg));
144 Inst.addOperand(MCOperand::createReg(Reg));
156 Inst.addOperand(MCOperand::createReg(Reg));
269 MI.addOperand(MCOperand::createImm(0));
278 MI.addOperand(MCOperand::createImm(SignExtend32<7>(sy)));
282 MI.addOperand(MCOperand::createImm(simm32));
300 MI.addOperand(MCOperand::createImm(0));
304 MI.addOperand(MCOperand
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/AsmParser/
H A DLanaiAsmParser.cpp394 Inst.addOperand(MCOperand::createImm(0));
397 MCOperand::createImm(static_cast<int32_t>(ConstExpr->getValue())));
399 Inst.addOperand(MCOperand::createExpr(Expr));
404 Inst.addOperand(MCOperand::createReg(getReg()));
435 Inst.addOperand(MCOperand::createReg(getMemBaseReg()));
438 Inst.addOperand(MCOperand::createImm(getMemOp()));
443 Inst.addOperand(MCOperand::createReg(getMemBaseReg()));
445 Inst.addOperand(MCOperand::createReg(getMemOffsetReg()));
446 Inst.addOperand(MCOperand::createImm(getMemOp()));
470 MCOperand
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.cpp28 NopInst.addOperand(MCOperand::createReg(ARM::R8));
29 NopInst.addOperand(MCOperand::createReg(ARM::R8));
30 NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
31 NopInst.addOperand(MCOperand::createReg(0));
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp174 MI.addOperand(MCOperand::createImm(0));
180 MI.addOperand(MCOperand::createInst(Inst));
282 MCOperand::createExpr(MCConstantExpr::create(-1, Context)));
286 MCOperand::createExpr(MCConstantExpr::create(-1, Context)));
403 MCOperand OPLow = MCOperand::createInst(MILow);
404 MCOperand OPHigh = MCOperand::createInst(MIHigh);
454 MCOperand::createExpr(MCConstantExpr::create(-1, getContext())));
462 MCOperand
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp252 const MCOperand &Offset, bool Is32BitAddress,
1051 Inst.addOperand(MCOperand::createImm(0));
1053 Inst.addOperand(MCOperand::createImm(CE->getValue()));
1055 Inst.addOperand(MCOperand::createExpr(Expr));
1067 Inst.addOperand(MCOperand::createReg(getGPR32Reg()));
1072 Inst.addOperand(MCOperand::createReg(getGPR32Reg()));
1077 Inst.addOperand(MCOperand::createReg(getGPR32Reg()));
1082 Inst.addOperand(MCOperand::createReg(getGPRMM16Reg()));
1087 Inst.addOperand(MCOperand::createReg(getGPRMM16Reg()));
1092 Inst.addOperand(MCOperand
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/MSP430/Disassembler/
H A DMSP430Disassembler.cpp80 MI.addOperand(MCOperand::createReg(Reg));
98 MI.addOperand(MCOperand::createReg(Reg));
124 MI.addOperand(MCOperand::createImm(Imm));
138 MI.addOperand(MCOperand::createImm((int16_t)Imm));
347 MI.addOperand(MCOperand::createImm(SignExtend32(Offset, 10)));
353 MI.addOperand(MCOperand::createImm(getCondCode(Cond)));
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp75 const MCOperand &Op0 = MI->getOperand(0);
76 const MCOperand &Op1 = MI->getOperand(1);
77 const MCOperand &Op2 = MI->getOperand(2);
78 const MCOperand &Op3 = MI->getOperand(3);
169 const MCOperand &Op0 = MI->getOperand(0); // Op1 == Op0
170 const MCOperand &Op2 = MI->getOperand(2);
770 const MCOperand &Op1 = MI->getOperand(0);
771 const MCOperand &Cn = MI->getOperand(1);
772 const MCOperand &Cm = MI->getOperand(2);
773 const MCOperand
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsAsmPrinter.h28 class MCOperand;
81 // lowerOperand - Convert a MachineOperand into the equivalent MCOperand.
82 bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DSIMCCodeEmitter.cpp47 uint32_t getLitEncoding(const MCOperand &MO, const MCOperandInfo &OpInfo,
62 /// \returns the encoding for an MCOperand.
63 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
224 uint32_t SIMCCodeEmitter::getLitEncoding(const MCOperand &MO,
334 const MCOperand &Op = MI.getOperand(i);
362 const MCOperand &MO = MI.getOperand(OpNo);
391 const MCOperand &MO = MI.getOperand(OpNo);
421 const MCOperand &MO = MI.getOperand(OpNo);
479 const MCOperand &MO,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/XCore/MCTargetDesc/
H A DXCoreInstPrinter.cpp77 const MCOperand &Op = MI->getOperand(OpNo);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp58 unsigned getX86RegNum(const MCOperand &MO) const;
68 void emitImmediate(const MCOperand &Disp, SMLoc Loc, unsigned ImmSize,
72 void emitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
167 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg);
168 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg);
169 const MCOperand &Disp = MI.getOperand(Op + X86::AddrDisp);
186 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg);
187 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg);
208 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg);
209 const MCOperand
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