/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600ISelLowering.cpp | 2077 SDValue &Sel, SDValue &Imm, 2151 // Check if the Imm slot is used. Taken from below. 2152 if (cast<ConstantSDNode>(Imm)->getZExtValue()) 2154 Imm = Src.getOperand(0); 2190 if (!Imm.getNode()) 2192 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Imm); 2196 Imm = DAG.getTargetConstant(ImmValue, SDLoc(ParentNode), MVT::i32); 2302 SDValue &Imm = Ops[ImmIdx]; local 2303 if (FoldOperand(Node, i, Src, Neg, Abs, Sel, Imm, DAG)) 2075 FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src, SDValue &Neg, SDValue &Abs, SDValue &Sel, SDValue &Imm, SelectionDAG &DAG) const argument
|
H A D | AMDGPUISelLowering.h | 187 bool isFPImmLegal(const APFloat &Imm, EVT VT,
|
H A D | GCNHazardRecognizer.cpp | 1004 const int64_t Imm = MI->getOperand(0).getImm(); 1005 AMDGPU::Waitcnt Decoded = AMDGPU::decodeWaitcnt(IV, Imm);
|
H A D | SIISelLowering.h | 292 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
|
/freebsd-13-stable/contrib/llvm-project/llvm/lib/ExecutionEngine/RuntimeDyld/ |
H A D | RuntimeDyldELF.cpp | 33 static void or32AArch64Imm(void *L, uint64_t Imm) { argument 34 or32le(L, (Imm & 0xFFF) << 10); 41 static void write32AArch64Addr(void *L, uint64_t Imm) { argument 42 uint32_t ImmLo = (Imm & 0x3) << 29; 43 uint32_t ImmHi = (Imm & 0x1FFFFC) << 3;
|
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmParser.cpp | 353 int64_t Imm; member in class:__anon4389::X86AsmParser::IntelExprStateMachine 377 TmpReg(0), Scale(0), Imm(0), Sym(nullptr), BracCount(0), 380 void addImm(int64_t imm) { Imm += imm; } 391 int64_t getImm() { return Imm + IC.execute(); } 1959 // .Imm gets lexed as a real. 2121 int64_t Imm = SM.getImm(); local 2123 const MCExpr *ImmDisp = MCConstantExpr::create(Imm, getContext()); 2124 if (Disp && Imm)
|
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonSplitDouble.cpp | 308 static inline int32_t profitImm(unsigned Imm) { argument 310 if (Imm == 0 || Imm == 0xFFFFFFFF)
|
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
H A D | AMDGPUBaseInfo.h | 698 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
|
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSEInstrInfo.cpp | 617 unsigned MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB, argument 632 AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
|
H A D | MipsISelLowering.h | 678 bool isFPImmLegal(const APFloat &Imm, EVT VT,
|
H A D | MipsInstrInfo.cpp | 854 int64_t Offset = RegImm->Imm;
|
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ExpandPseudoInsts.cpp | 120 uint64_t Imm = MI.getOperand(1).getImm(); local 130 AArch64_IMM::expandMOVImm(Imm, BitSize, Insn);
|
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineCalls.cpp | 750 uint8_t Imm = CInt->getZExtValue(); local 751 uint8_t ZMask = Imm & 0xf; 752 uint8_t DestLane = (Imm >> 4) & 0x3; 753 uint8_t SourceLane = (Imm >> 6) & 0x3; 3011 unsigned Imm = C->getZExtValue(); local 3020 APInt(2, (Imm & 0x01) ? 2 : 1)); 3029 APInt(2, (Imm & 0x10) ? 2 : 1));
|
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 2401 bool llvm::isIntS16Immediate(SDNode *N, int16_t &Imm) { argument 2405 Imm = (int16_t)cast<ConstantSDNode>(N)->getZExtValue(); 2407 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue(); 2409 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue(); 2411 bool llvm::isIntS16Immediate(SDValue Op, int16_t &Imm) { argument 2412 return isIntS16Immediate(Op.getNode(), Imm); 2448 int16_t Imm = 0; 2454 if (isIntS16Immediate(N.getOperand(1), Imm) && 2455 (!EncodingAlignment || isAligned(*EncodingAlignment, Imm))) 2464 if (isIntS16Immediate(N.getOperand(1), Imm) 2598 int16_t Imm; local 12708 unsigned Imm = MI.getOperand(1).getImm(); local 16288 shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const argument 16576 isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const argument [all...] |
/freebsd-13-stable/contrib/llvm-project/clang/lib/CodeGen/ |
H A D | CGBuiltin.cpp | 11213 uint64_t Imm = cast<llvm::ConstantInt>(Ops[2])->getZExtValue() & 0x7; 11216 switch (Imm) { 11824 auto getCmpIntrinsicCall = [this, &Ops](Intrinsic::ID ID, unsigned Imm) { 11825 Ops.push_back(llvm::ConstantInt::get(Int8Ty, Imm)); 12605 unsigned Imm = cast<llvm::ConstantInt>(Ops[2])->getZExtValue(); 12611 Indices[i] = ((Imm >> (i % 8)) & 0x1) ? NumElts + i : i; 12620 uint32_t Imm = cast<llvm::ConstantInt>(Ops[1])->getZExtValue(); 12625 Imm = (Imm & 0xff) * 0x01010101; 12630 Indices[l + i] = l + (Imm [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZInstrInfo.cpp | 949 uint64_t Imm = MI.getOperand(2).getImm() << And.ImmLSB; local 951 Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB); 953 if (isRxSBGMask(Imm, And.RegSize, Start, End)) {
|
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InstructionSelector.cpp | 483 int64_t Imm = *COff; local 484 if (isInt<32>(Imm)) { // Check for displacement overflow. 485 AM.Disp = static_cast<int32_t>(Imm);
|
H A D | X86FastISel.cpp | 3689 uint64_t Imm = CI->getZExtValue(); 3690 if (Imm == 0) { 3723 if (isUInt<32>(Imm)) 3725 else if (isInt<32>(Imm)) 3732 return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm);
|
H A D | X86ISelLowering.cpp | 5088 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, 5091 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 5133 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm, 9070 SDValue Imm = DAG.getConstant(Immediate, dl, ImmVT); 9072 DstVec = DAG.getBitcast(VecVT, Imm); 10951 unsigned Imm = 0; 10952 Imm |= (Mask[0] < 0 ? 0 : Mask[0]) << 0; 10953 Imm |= (Mask[1] < 0 ? 1 : Mask[1]) << 2; 10954 Imm |= (Mask[2] < 0 ? 2 : Mask[2]) << 4; 10955 Imm | [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | CombinerHelper.cpp | 1380 MatchInfo.Imm = MaybeImmVal->Value + MaybeImm2Val->Value; 1390 auto NewOffset = MIB.buildConstant(OffsetTy, MatchInfo.Imm);
|
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64InstPrinter.cpp | 918 unsigned Imm, raw_ostream &O) { 923 O << "#" << Imm; local 917 printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm, raw_ostream &O) argument
|
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMLoadStoreOptimizer.cpp | 1498 int Imm = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift); variable 1503 .addImm(Imm) 1522 int Imm = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift); variable 1528 .addImm(Imm)
|
/freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | GlobalISelEmitter.cpp | 2668 int64_t Imm; 2671 ImmRenderer(unsigned InsnID, int64_t Imm) 2672 : OperandRenderer(OR_Imm), InsnID(InsnID), Imm(Imm) {} 2680 << MatchTable::IntValue(InsnID) << MatchTable::Comment("Imm") 2681 << MatchTable::IntValue(Imm) << MatchTable::LineBreak; 5089 "Imm", "", Filter); 5320 << " bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const " 5322 << " bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) " 5325 "&Imm) cons [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 2542 unsigned Imm = fieldFromInstruction(Insn, 9, 1); local 2561 Inst.addOperand(MCOperand::createImm(Imm)); 6003 unsigned Imm = fieldFromInstruction(Insn, 11, 1) | local 6013 Inst, Imm, Address, Decoder))) 6026 Inst, Imm, Address, Decoder))) 6185 unsigned Imm = 0; local 6194 Imm |= (CurBit << i); 6198 Imm |= 1U << i; 6203 Inst.addOperand(MCOperand::createImm(Imm));
|
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | TargetInstrInfo.cpp | 1180 Offset = RegImm->Imm;
|