/freebsd-13-stable/contrib/llvm-project/clang/lib/Driver/ToolChains/ |
H A D | MinGW.cpp | 360 llvm::SmallString<1024> LibDir(Base); 406 Base = getDriver().SysRoot; 410 Base = std::string(llvm::sys::path::parent_path(TargetSubdir.get())); 412 Base = std::string(llvm::sys::path::parent_path( 415 Base = std::string( 418 Base += llvm::sys::path::get_separator(); 420 // GccLibDir must precede Base/lib so that the 424 (Base + Arch + llvm::sys::path::get_separator() + "lib").str()); 425 getFilePaths().push_back(Base + "lib"); 427 getFilePaths().push_back(Base [all...] |
/freebsd-13-stable/contrib/libarchive/libarchive/ |
H A D | archive_ppmd8_private.h | 62 Byte *Base, *LoUnit, *HiUnit, *Text, *UnitsStart; member in struct:__anon1086 90 #define Ppmd8_WasAllocated(p) ((p)->Base != NULL) 102 #define Ppmd8_GetPtr(p, offs) ((void *)((p)->Base + (offs))) 134 /* Base Functions */ 139 #define Ppmd7_WasAllocated(p) ((p)->Base != NULL)
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/MSP430/ |
H A D | MSP430AsmPrinter.cpp | 109 const MachineOperand &Base = MI->getOperand(OpNum); local 115 if (Disp.isImm() && Base.getReg() == MSP430::SR) 120 if (Base.getReg() != MSP430::SR && Base.getReg() != MSP430::PC) {
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/Transforms/Scalar/ |
H A D | Reassociate.h | 60 Value *Base; member in struct:llvm::reassociate::Factor 63 Factor(Value *Base, unsigned Power) : Base(Base), Power(Power) {} argument
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUAliasAnalysis.cpp | 99 const Value *Base = GetUnderlyingObject(Loc.Ptr, DL); local 100 AS = Base->getType()->getPointerAddressSpace(); 105 if (const GlobalVariable *GV = dyn_cast<GlobalVariable>(Base)) { 108 } else if (const Argument *Arg = dyn_cast<Argument>(Base)) {
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H A D | AMDGPUPerfHintAnalysis.cpp | 81 const Value *Base; member in struct:__anon3925::AMDGPUPerfHint::MemAccessInfo 83 MemAccessInfo() : V(nullptr), Base(nullptr), Offset(0) {} 89 << "Base: " << *Base << " Offset: " << Offset << '\n'; 321 if (MAI.Base) 338 MAI.Base = GetPointerBaseWithConstantOffset(MO, MAI.Offset, *DL); 354 if (!Base || !Reference.Base || Base != Reference.Base) [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/DebugInfo/DWARF/ |
H A D | DWARFUnit.h | 44 /// Base class describing the header of any kind of "unit." Some information 175 uint64_t Base = 0; member in struct:llvm::StrOffsetsContributionDescriptor 181 StrOffsetsContributionDescriptor(uint64_t Base, uint64_t Size, argument 183 : Base(Base), Size(Size), FormParams({Version, 0, Format}) {} 304 void setAddrOffsetSection(const DWARFSection *AOS, uint64_t Base) { argument 306 AddrOffsetSectionBase = Base; 312 void setRangesSection(const DWARFSection *RS, uint64_t Base) { argument 314 RangeSectionBase = Base; 316 void setLocSection(const DWARFSection *LS, uint64_t Base) { argument [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/DebugInfo/DWARF/ |
H A D | DWARFDebugLoc.cpp | 29 Optional<object::SectionedAddress> Base; member in class:__anon3621::DWARFLocationInterpreter 34 Optional<object::SectionedAddress> Base, 36 : Base(Base), LookupAddr(std::move(LookupAddr)) {} 55 Base = LookupAddr(E.Value0); 56 if (!Base) 81 if (!Base) { 84 "Base address not defined"); 86 DWARFAddressRange Range{Base->Address + E.Value0, Base 33 DWARFLocationInterpreter( Optional<object::SectionedAddress> Base, std::function<Optional<object::SectionedAddress>(uint32_t)> LookupAddr) argument [all...] |
/freebsd-13-stable/contrib/llvm-project/clang/lib/Driver/ |
H A D | Multilib.cpp | 172 static Multilib compose(const Multilib &Base, const Multilib &New) { argument 174 llvm::sys::path::append(GCCSuffix, "/", Base.gccSuffix(), New.gccSuffix()); 176 llvm::sys::path::append(OSSuffix, "/", Base.osSuffix(), New.osSuffix()); 178 llvm::sys::path::append(IncludeSuffix, "/", Base.includeSuffix(), 185 Flags.insert(Flags.end(), Base.flags().begin(), Base.flags().end()); 199 for (const auto &Base : *this) { 200 Multilib MO = compose(Base, New);
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/Analysis/ |
H A D | PostDominators.h | 30 using Base = PostDomTreeBase<BasicBlock>; 39 using Base::dominates;
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H A D | PtrUseVisitor.h | 209 using Base = InstVisitor<DerivedT>; 287 return Base::visitIntrinsicInst(II); 299 Base::visitCallBase(CB);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMLoadStoreOptimizer.cpp | 172 unsigned Base, unsigned WordOffset, 176 int Offset, unsigned Base, bool BaseKill, unsigned Opcode, 182 int Offset, unsigned Base, bool BaseKill, unsigned Opcode, 485 const DebugLoc &DL, unsigned Base, 496 if (MBBI->readsRegister(Base)) { 516 if (Offset >= 0 && !(IsStore && InstrSrcReg == Base)) 552 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBi8), Base) 554 .addReg(Base) 561 if (MBBI->killsRegister(Base) || MBBI->definesRegister(Base)) 483 UpdateBaseRegUses(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned Base, unsigned WordOffset, ARMCC::CondCodes Pred, unsigned PredReg) argument 625 CreateLoadStoreMulti( MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, int Offset, unsigned Base, bool BaseKill, unsigned Opcode, ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, ArrayRef<std::pair<unsigned, bool>> Regs, ArrayRef<MachineInstr*> Instrs) argument 832 CreateLoadStoreDouble( MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, int Offset, unsigned Base, bool BaseKill, unsigned Opcode, ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, ArrayRef<std::pair<unsigned, bool>> Regs, ArrayRef<MachineInstr*> Instrs) const argument 903 Register Base = getLoadStoreBaseOp(*First).getReg(); local 1273 Register Base = BaseOP.getReg(); local [all...] |
H A D | ARMISelDAGToDAG.cpp | 102 bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm); 103 bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc); 118 bool SelectAddrOffsetNone(SDValue N, SDValue &Base); 119 bool SelectAddrMode3(SDValue N, SDValue &Base, 123 bool IsAddressingMode5(SDValue N, SDValue &Base, SDValue &Offset, bool FP16); 124 bool SelectAddrMode5(SDValue N, SDValue &Base, SDValue &Offset); 125 bool SelectAddrMode5FP16(SDValue N, SDValue &Base, SDValue &Offset); 132 bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset); 133 bool SelectThumbAddrModeRRSext(SDValue N, SDValue &Base, SDValue &Offset); 134 bool SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base, 646 SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm) argument 699 SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) argument 883 SelectAddrOffsetNone(SDValue N, SDValue &Base) argument 888 SelectAddrMode3(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) argument 964 IsAddressingMode5(SDValue N, SDValue &Base, SDValue &Offset, bool FP16) argument 1023 SelectAddrMode5(SDValue N, SDValue &Base, SDValue &Offset) argument 1028 SelectAddrMode5FP16(SDValue N, SDValue &Base, SDValue &Offset) argument 1108 SelectThumbAddrModeRRSext(SDValue N, SDValue &Base, SDValue &Offset) argument 1124 SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset) argument 1132 SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base, SDValue &OffImm) argument 1170 SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base, SDValue &OffImm) argument 1176 SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base, SDValue &OffImm) argument 1182 SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base, SDValue &OffImm) argument 1187 SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm) argument 1234 SelectTAddrModeImm7(SDValue N, SDValue &Base, SDValue &OffImm) argument 1261 SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm) argument 1318 SelectT2AddrModeImm8(SDValue N, SDValue &Base, SDValue &OffImm) argument 1344 SelectT2AddrModeImm8(SDValue N, SDValue &Base, SDValue &OffImm) argument 1389 SelectT2AddrModeImm7(SDValue N, SDValue &Base, SDValue &OffImm) argument 1467 SelectT2AddrModeSoReg(SDValue N, SDValue &Base, SDValue &OffReg, SDValue &ShImm) argument 1527 SelectT2AddrModeExclusive(SDValue N, SDValue &Base, SDValue &OffImm) argument 1623 SDValue Base = LD->getBasePtr(); local 1633 SDValue Base = LD->getBasePtr(); local 1664 SDValue Base = LD->getBasePtr(); local 1712 SDValue Base = LD->getBasePtr(); local 1732 SDValue Chain, Base, Offset; local 3698 SDValue Base, RegOffset, ImmOffset; local 3727 SDValue Base, RegOffset, ImmOffset; local [all...] |
H A D | ARMParallelDSP.cpp | 393 auto SafeToPair = [&](LoadInst *Base, LoadInst *Offset) { 394 bool BaseFirst = Base->comesBefore(Offset); 395 LoadInst *Dominator = BaseFirst ? Base : Offset; 396 LoadInst *Dominated = BaseFirst ? Offset : Base; 412 for (auto *Base : Loads) { 414 if (Base == Offset || OffsetLoads.count(Offset)) 417 if (AreSequentialAccesses<LoadInst>(Base, Offset, *DL, *SE) && 418 SafeToPair(Base, Offset)) { 419 LoadPairs[Base] = Offset; 740 LoadInst *Base local [all...] |
/freebsd-13-stable/contrib/llvm-project/clang/lib/AST/ |
H A D | VTableBuilder.cpp | 120 void ComputeBaseOffsets(BaseSubobject Base, bool IsVirtual, 130 void dump(raw_ostream &Out, BaseSubobject Base, 230 if (Element.Base->isVirtual()) { 232 QualType VBaseType = Element.Base->getType(); 245 const CXXRecordDecl *Base = Element.Base->getType()->getAsCXXRecordDecl(); local 247 NonVirtualOffset += Layout.getBaseClassOffset(Base); 306 // const T *Base::foo(); 324 FinalOverriders::ComputeBaseOffsets(BaseSubobject Base, bool IsVirtual, argument 329 const CXXRecordDecl *RD = Base 377 dump(raw_ostream &Out, BaseSubobject Base, VisitedVirtualBasesSetTy &VisitedVirtualBases) argument 588 VCallAndVBaseOffsetBuilder(const ItaniumVTableContext &VTables, const CXXRecordDecl *MostDerivedClass, const CXXRecordDecl *LayoutClass, const FinalOverriders *Overriders, BaseSubobject Base, bool BaseIsVirtual, CharUnits OffsetInLayoutClass) argument 614 AddVCallAndVBaseOffsets(BaseSubobject Base, bool BaseIsVirtual, CharUnits RealBaseOffset) argument 679 AddVCallOffsets(BaseSubobject Base, CharUnits VBaseOffset) argument 1208 ComputeThisAdjustmentBaseOffset( BaseSubobject Base, BaseSubobject Derived) const argument 1434 AddMethods( BaseSubobject Base, CharUnits BaseOffsetInLayoutClass, const CXXRecordDecl *FirstBaseInPrimaryBaseChain, CharUnits FirstBaseOffsetInLayoutClass, PrimaryBasesSetVectorTy &PrimaryBases) argument 1637 LayoutPrimaryAndSecondaryVTables( BaseSubobject Base, bool BaseIsMorallyVirtual, bool BaseIsVirtualInLayoutClass, CharUnits OffsetInLayoutClass) argument 1734 LayoutSecondaryVTables(BaseSubobject Base, bool BaseIsMorallyVirtual, CharUnits OffsetInLayoutClass) argument 1908 const BaseSubobject &Base = AP.first; local 2047 const BaseSubobject &Base = local 2933 isDirectVBase(const CXXRecordDecl *Base, const CXXRecordDecl *RD) argument 2941 AddMethods(BaseSubobject Base, unsigned BaseDepth, const CXXRecordDecl *LastVBase, BasesSetVectorTy &VisitedBases) argument 3310 const CXXRecordDecl *Base = B.getType()->getAsCXXRecordDecl(); local 3439 const CXXRecordDecl *Base = BS.getType()->getAsCXXRecordDecl(); local 3473 const CXXRecordDecl *Base = BSO.getBase(); local [all...] |
H A D | ASTTypeTraits.cpp | 51 bool ASTNodeKind::isBaseOf(NodeKindId Base, NodeKindId Derived, argument 53 if (Base == NKI_None || Derived == NKI_None) return false; 55 while (Derived != Base && Derived != NKI_None) { 61 return Derived == Base; 105 #define TYPE(Class, Base) \ 107 #define ABSTRACT_TYPE(Class, Base)
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/freebsd-13-stable/contrib/googletest/googletest/test/ |
H A D | googletest-port-test.cc | 90 class Base { class in namespace:testing::internal 94 Base() : member_(0) {} function in class:testing::internal::Base 95 explicit Base(int n) : member_(n) {} function in class:testing::internal::Base 96 virtual ~Base() {} 103 class Derived : public Base { 105 explicit Derived(int n) : Base(n) {} 110 EXPECT_TRUE(&derived == ::testing::internal::ImplicitCast_<Base*>(&derived)); 115 Base base = ::testing::internal::ImplicitCast_<Base>(derived); 122 operator Base() { [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
H A D | StraightLineStrengthReduce.cpp | 113 : CandidateKind(CT), Base(B), Index(Idx), Stride(S), Ins(I) {} 117 const SCEV *Base = nullptr; member in struct:__anon4716::StraightLineStrengthReduce::Candidate 135 // <Base: a, Index: 1, Stride: b + 2> 139 // <Base: b, Index: 2, Stride: a + 1> 195 // Splits LHS into Base + Index and, if succeeds, calls 221 void factorArrayIndex(Value *ArrayIdx, const SCEV *Base, uint64_t ElementSize, 263 // They must have the same type too. Basis.Base == C.Base doesn't 269 Basis.Base == C.Base 283 isAddFoldable(const SCEV *Base, ConstantInt *Index, Value *Stride, TargetTransformInfo *TTI) argument 483 factorArrayIndex(Value *ArrayIdx, const SCEV *Base, uint64_t ElementSize, GetElementPtrInst *GEP) argument [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/Support/ |
H A D | OnDiskHashTable.h | 278 const unsigned char *const Base; member in class:llvm::OnDiskChainedHashTable 291 const unsigned char *Base, 294 Base(Base), InfoObj(InfoObj) { 316 const unsigned char *getBase() const { return Base; } 364 const unsigned char *Items = Base + Offset; 413 /// \param Base is the point from which all offsets into the structure are 417 const unsigned char *const Base, 419 assert(Buckets > Base); 423 Buckets, Base, InfoOb 289 OnDiskChainedHashTable(offset_type NumBuckets, offset_type NumEntries, const unsigned char *Buckets, const unsigned char *Base, const Info &InfoObj = Info()) argument 416 Create(const unsigned char *Buckets, const unsigned char *const Base, const Info &InfoObj = Info()) argument 492 OnDiskIterableChainedHashTable(offset_type NumBuckets, offset_type NumEntries, const unsigned char *Buckets, const unsigned char *Payload, const unsigned char *Base, const Info &InfoObj = Info()) argument 603 Create(const unsigned char *Buckets, const unsigned char *const Payload, const unsigned char *const Base, const Info &InfoObj = Info()) argument [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiMemAluCombiner.cpp | 242 MachineOperand Base = MemInstr->getOperand(1); local 261 InstrBuilder.addReg(Base.getReg(), getKillRegState(true)); 286 const MachineOperand &Base, 298 if (!isSameOperand(Dest, Base) || !isSameOperand(Dest, Op1)) 331 MachineOperand *Base = &MemInstr->getOperand(1); local 348 if (isSuitableAluInstr(IsSpls, First, *Base, *Offset)) { 354 if (InstrUsesReg(First, Base)) 285 isSuitableAluInstr(bool IsSpls, const MbbIterator &AluIter, const MachineOperand &Base, const MachineOperand &Offset) argument
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64MachObjectWriter.cpp | 322 const MCSymbol *Base = Asm.getAtom(*Symbol); local 325 assert(!Symbol->isVariable() || Base); 333 Base = nullptr; 339 if (Base) { 340 RelSymbol = Base; 343 if (Base != Symbol) 345 Layout.getSymbolOffset(*Symbol) - Layout.getSymbolOffset(*Base);
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/freebsd-13-stable/contrib/llvm-project/compiler-rt/lib/xray/ |
H A D | xray_segmented_array.h | 156 auto Base = &S->Data; variable 157 auto AlignedOffset = Base + (RelOff * AlignedElementStorageSize); 371 auto Base = &Tail->Data; variable 372 auto AlignedOffset = Base + (Offset * AlignedElementStorageSize); 374 reinterpret_cast<unsigned char *>(Base) + SegmentSize); 403 auto Base = &Tail->Data; variable 404 auto AlignedOffset = Base + (Offset * AlignedElementStorageSize); 423 auto Base = &S->Data; variable 424 auto AlignedOffset = Base + (Offset * AlignedElementStorageSize);
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/freebsd-13-stable/contrib/llvm-project/libcxx/src/filesystem/ |
H A D | filesystem_common.h | 295 using Base = time_util_base<FileTimeT, TimeT>; 296 using Base::max_nsec; 297 using Base::max_seconds; 298 using Base::min_nsec_timespec; 299 using Base::min_seconds; 301 using typename Base::fs_duration; 302 using typename Base::fs_microseconds; 303 using typename Base::fs_nanoseconds; 304 using typename Base::fs_seconds;
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/freebsd-13-stable/contrib/llvm-project/clang/lib/CodeGen/ |
H A D | CGVTT.cpp | 130 BaseSubobject Base) { 131 BaseSubobjectPairTy ClassSubobjectPair(RD, Base); 156 BaseSubobject Base) { 158 SecondaryVirtualPointerIndices.find(std::make_pair(RD, Base)); 175 I = SecondaryVirtualPointerIndices.find(std::make_pair(RD, Base)); 129 getSubVTTIndex(const CXXRecordDecl *RD, BaseSubobject Base) argument 155 getSecondaryVirtualPointerIndex(const CXXRecordDecl *RD, BaseSubobject Base) argument
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86FixupLEAs.cpp | 319 static inline bool hasInefficientLEABaseReg(const MachineOperand &Base, argument 321 return Base.isReg() && isInefficientLEAReg(Base.getReg()) && Index.isReg() && 372 const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg); local 383 Register BaseReg = Base.getReg(); 412 .addReg(Base.getReg(), RegState::Implicit) 432 .addReg(BaseReg).addReg(Base.getReg(), RegState::Implicit); 443 .addReg(Base.getReg(), RegState::Implicit); 501 const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg); local 511 const Register SrcR1 = Base 551 const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg); local [all...] |