/freebsd-12-stable/sys/dev/bhnd/nvram/ |
H A D | bhnd_nvram_value.h | 235 int32_t i32[2]; /**< 32-bit signed data */ member in union:bhnd_nvram_val::__anon12332
|
H A D | bhnd_nvram_value_prf.c | 630 int32_t i32; member in union:__anon12334
|
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 175 addRegisterClass(MVT::i32, &X86::GR32RegClass); 183 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 186 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 187 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 203 setOperationAction(ISD::ABS , MVT::i32 , Custom); 210 setOperationAction(ShiftOp , MVT::i32 , Custom); 224 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); 225 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Custom); 235 // SSE has no i16 to fp conversion, only i32. We promote in the handler 240 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custo [all...] |
H A D | X86FastISel.cpp | 255 if (RetVT != MVT::i32 && RetVT != MVT::i64) 342 case MVT::i32: 510 case MVT::i32: 660 // Handle 'null' like i32/i64 0. 675 case MVT::i32: Opc = X86::MOV32mi; break; 1232 assert(DstVT == MVT::i32 && "X86 should always ext to i32"); 1349 case MVT::i32: return X86::CMP32rr; 1378 case MVT::i32: 1398 // Handle 'null' like i32/i6 [all...] |
H A D | X86CallingConv.cpp | 220 LocVT = MVT::i32;
|
H A D | X86TargetTransformInfo.cpp | 860 { ISD::ADD, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 864 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 1963 { ISD::BITREVERSE, MVT::i32, 3 }, 2119 { ISD::CTLZ, MVT::i32, 1 }, 2127 { ISD::CTPOP, MVT::i32, 1 }, 2139 { ISD::BITREVERSE, MVT::i32, 14 }, 2142 { ISD::CTLZ, MVT::i32, 4 }, // BSR+XOR or BSR+XOR+CMOV 2145 { ISD::CTPOP, MVT::i32, 8 }, 2148 { ISD::SADDO, MVT::i32, 1 }, 2151 { ISD::UADDO, MVT::i32, [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/Support/ |
H A D | MachineValueType.h | 43 i32 = 5, // This is a 32 bit integer value 92 v1i32 = 43, // 1 x i32 93 v2i32 = 44, // 2 x i32 94 v3i32 = 45, // 3 x i32 95 v4i32 = 46, // 4 x i32 96 v5i32 = 47, // 5 x i32 97 v8i32 = 48, // 8 x i32 98 v16i32 = 49, // 16 x i32 99 v32i32 = 50, // 32 x i32 100 v64i32 = 51, // 64 x i32 [all...] |
/freebsd-12-stable/crypto/openssl/crypto/sha/asm/ |
H A D | sha512-armv8.pl | 404 add.i32 $W0,$W0,@MSG[0] 415 add.i32 $W0,$W0,@MSG[0] 421 add.i32 $W1,$W1,@MSG[1] 427 add.i32 $W0,$W0,@MSG[2] 433 add.i32 $W1,$W1,@MSG[3] 438 add.i32 $ABCD,$ABCD,$ABCD_SAVE 439 add.i32 $EFGH,$EFGH,$EFGH_SAVE
|
/freebsd-12-stable/sys/cddl/contrib/opensolaris/uts/common/os/ |
H A D | fm.c | 231 uint32_t i32; local 277 (void) nvpair_value_int32(nvp, (void *)&i32); 278 c = fm_printf(d + 1, c, cols, "%x", i32); 282 (void) nvpair_value_uint32(nvp, &i32); 283 c = fm_printf(d + 1, c, cols, "%x", i32);
|
/freebsd-12-stable/secure/lib/libcrypto/arm/ |
H A D | bsaes-armv7.S | 1327 vmov.i32 q0, #0 1328 vmov.i32 q1, #0 1400 vmov.i32 q8,#1 @ compose 1<<96 1460 vmov.i32 q8, #1 @ compose 1<<96 1508 vmov.i32 q0, #0 1509 vmov.i32 q1, #0 1563 vmov.i32 q0, #0 1564 vmov.i32 q1, #0 2030 vmov.i32 q0, #0 2031 vmov.i32 q [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonSubtarget.h | 226 static MVT Types[] = { MVT::i8, MVT::i16, MVT::i32 };
|
H A D | HexagonISelDAGToDAGHVX.cpp | 1044 DAG.getTargetConstant(Hexagon::HvxWRRegClassID, dl, MVT::i32), 1045 Lo, DAG.getTargetConstant(Hexagon::vsub_lo, dl, MVT::i32), 1046 Hi, DAG.getTargetConstant(Hexagon::vsub_hi, dl, MVT::i32), 1103 dl, MVT::i32); 1108 SDValue S = DAG.getTargetConstant(MinSrc, dl, MVT::i32); 1109 Results.push(Hexagon::A2_tfrsi, MVT::i32, {S}); 1413 SDValue Idx = DAG.getConstant(M, dl, MVT::i32); 1926 Results.push(Hexagon::A2_tfrsi, MVT::i32, 1927 { DAG.getTargetConstant(S, dl, MVT::i32) }); 2090 SDValue C = DAG.getTargetConstant(S, dl, MVT::i32); [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.h | 98 return MVT::i32;
|
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.h | 104 return MVT::i32;
|
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRISelLowering.cpp | 76 setOperationAction(ISD::ADD, MVT::i32, Custom); 98 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 104 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 108 setOperationAction(ISD::SETCC, MVT::i32, Custom); 357 case MVT::i32: 537 if (VT == MVT::i32) { 557 SDValue LHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS, 559 SDValue LHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS, 571 SDValue RHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS, 573 SDValue RHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RH [all...] |
/freebsd-12-stable/sys/compat/freebsd32/ |
H A D | freebsd32_misc.c | 530 struct itimerval32 i32; local 534 error = copyin(uap->itv, &i32, sizeof(i32)); 537 TV_CP(i32, itv, it_interval); 538 TV_CP(i32, itv, it_value); 545 TV_CP(oitv, i32, it_interval); 546 TV_CP(oitv, i32, it_value); 547 return (copyout(&i32, uap->oitv, sizeof(i32))); 554 struct itimerval32 i32; local [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.h | 315 // Operand 1: the second operand of <op>, in the high bits of an i32 317 // Operand 2: how many bits to rotate the i32 left to bring the first 336 // Operand 1: the compare value, in the low bits of an i32 337 // Operand 2: the swap value, in the low bits of an i32 338 // Operand 3: how many bits to rotate the i32 left to bring the first 398 return MVT::i32; 403 return MVT::i32;
|
/freebsd-12-stable/contrib/ntp/sntp/libevent/test/ |
H A D | regress_util.c | 691 ev_int32_t i32; local 707 tt_int_op(sizeof(i32), ==, 4); 735 i32 = EV_INT32_MAX; 737 tt_assert(i32 > 0); 739 /* i32++; */ 741 /* tt_assert(i32 == EV_INT32_MIN); */ 742 /* tt_assert(i32 < 0); */
|
/freebsd-12-stable/contrib/libevent/test/ |
H A D | regress_util.c | 691 ev_int32_t i32; local 707 tt_int_op(sizeof(i32), ==, 4); 735 i32 = EV_INT32_MAX; 737 tt_assert(i32 > 0); 739 /* i32++; */ 741 /* tt_assert(i32 == EV_INT32_MIN); */ 742 /* tt_assert(i32 < 0); */
|
/freebsd-12-stable/crypto/openssl/crypto/aes/asm/ |
H A D | bsaes-armv7.pl | 1371 vmov.i32 q0, #0 1372 vmov.i32 q1, #0 1452 vmov.i32 @XMM[8],#1 @ compose 1<<96 1512 vmov.i32 @XMM[8], #1 @ compose 1<<96 1560 vmov.i32 q0, #0 1561 vmov.i32 q1, #0 1615 vmov.i32 q0, #0 1616 vmov.i32 q1, #0 2020 vmov.i32 q0, #0 2021 vmov.i32 q [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeDAG.cpp | 304 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 443 TLI.isTypeLegal(MVT::i32)) { 446 SDLoc(CFP), MVT::i32); 460 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) { 465 SDValue Lo = DAG.getConstant(IntVal.trunc(32), dl, MVT::i32); 466 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), dl, MVT::i32); 642 // TRUNCSTORE:i16 i32 -> STORE i16 2132 case MVT::i32: LC = Call_I32; break; 2189 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break; 2356 if (SrcVT == MVT::i32 [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelDAGToDAG.cpp | 273 Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, 0,
|
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.h | 510 return MVT::i32;
|
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyAsmPrinter.cpp | 60 for (MVT T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64, MVT::v16i8, MVT::v8i16,
|
H A D | WebAssemblyExplicitLocals.cpp | 153 return MVT::i32;
|