Lines Matching refs:i32
304 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
443 TLI.isTypeLegal(MVT::i32)) {
446 SDLoc(CFP), MVT::i32);
460 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
465 SDValue Lo = DAG.getConstant(IntVal.trunc(32), dl, MVT::i32);
466 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), dl, MVT::i32);
642 // TRUNCSTORE:i16 i32 -> STORE i16
2132 case MVT::i32: LC = Call_I32; break;
2189 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2356 if (SrcVT == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2377 SDValue SignBit = DAG.getConstant(0x80000000u, dl, MVT::i32);
2378 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2386 SDValue InitialHi = DAG.getConstant(0x43300000u, dl, MVT::i32);
2447 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2673 case MVT::i32:
2788 Results.push_back(DAG.getConstant(0, dl, MVT::i32));
3049 // If original node was v4i64 and the new EltVT is i32,
4187 case MVT::i32:
4572 // e.g. v2i64 = extract_vector_elt x:v2i64, y:i32
4577 // (v2i32 build_vector (i32 (extract_vector_elt castx, (2 * y))),
4578 // (i32 (extract_vector_elt castx, (2 * y + 1)))
4616 // e.g. v2i64 = insert_vector_elt x:v2i64, y:i64, z:i32