Searched refs:Mask (Results 76 - 100 of 334) sorted by relevance

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/freebsd-12-stable/contrib/llvm-project/llvm/tools/llvm-mca/Views/
H A DBottleneckAnalysis.h108 // `getResourceStateIndex(Mask)` to processor resource identifiers.
260 void addResourceDep(unsigned From, unsigned To, uint64_t Mask, argument
262 addDependency(From, To, {DependencyEdge::DT_RESOURCE, Mask, Cost});
318 void addResourceDep(unsigned From, unsigned To, uint64_t Mask, unsigned Cy);
/freebsd-12-stable/sys/contrib/dev/acpica/include/
H A Dacmacros.h465 #define ACPI_REGISTER_PREPARE_BITS(Val, Pos, Mask) \
466 ((Val << Pos) & Mask)
468 #define ACPI_REGISTER_INSERT_VALUE(Reg, Pos, Mask, Val) \
469 Reg = (Reg & (~(Mask))) | ACPI_REGISTER_PREPARE_BITS(Val, Pos, Mask)
471 #define ACPI_INSERT_BITS(Target, Mask, Source) \
472 Target = ((Target & (~(Mask))) | (Source & Mask))
476 #define ACPI_GET_BITS(SourcePtr, Position, Mask) \
477 ((*(SourcePtr) >> (Position)) & (Mask))
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FloatingPoint.cpp102 unsigned Mask; member in struct:__anon5456::FPS::LiveBundle
112 LiveBundle() : Mask(0), FixCount(0) {}
115 bool isFixed() const { return !Mask || FixCount; }
127 unsigned Mask = 0; local
133 Mask |= 1 << (Reg - X86::FP0);
141 return Mask;
270 /// Adjust the live registers to be the set in Mask.
271 void adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I);
360 CallingConv::X86_RegCall) && (Bundle.Mask && !Bundle.FixCount)) {
367 assert((Bundle.Mask
401 const unsigned Mask = calcLiveInMask(&MBB, false); local
534 unsigned Mask = calcLiveInMask(MBB, /*RemoveFPs=*/true); local
890 adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I) argument
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H A DX86ISelDAGToDAG.cpp448 APInt Mask = Val | CurDAG->computeKnownBits(N->getOperand(0)).Zero;
449 return Mask.countTrailingOnes() >= Width;
518 bool tryVPTESTM(SDNode *Root, SDValue Setcc, SDValue Mask);
1632 uint64_t Mask,
1642 Mask != (0xffu << ScaleLog))
1682 int64_t Mask = cast<ConstantSDNode>(N->getOperand(1))->getSExtValue(); local
1690 isUInt<32>(Mask)) {
1720 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, DL, VT);
1768 uint64_t Mask,
1776 unsigned MaskLZ = countLeadingZeros(Mask);
1631 foldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N, uint64_t Mask, SDValue Shift, SDValue X, X86ISelAddressMode &AM) argument
1767 foldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N, uint64_t Mask, SDValue Shift, SDValue X, X86ISelAddressMode &AM) argument
1854 foldMaskedShiftToBEXTR(SelectionDAG &DAG, SDValue N, uint64_t Mask, SDValue Shift, SDValue X, X86ISelAddressMode &AM, const X86Subtarget &Subtarget) argument
2026 uint64_t Mask = And.getConstantOperandVal(1) >> N.getConstantOperandVal(1); local
2176 uint64_t Mask = N.getConstantOperandVal(1); local
3403 SDValue Mask = Node->getOperand(1); local
5076 uint64_t Mask = C->getZExtValue(); local
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp1542 SDValue Mask = MLD->getMask(); local
1547 // Split Mask operand
1549 if (Mask.getOpcode() == ISD::SETCC) {
1550 SplitVecRes_SETCC(Mask.getNode(), MaskLo, MaskHi);
1552 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1553 GetSplitVector(Mask, MaskLo, MaskHi);
1555 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1609 SDValue Mask = MGT->getMask(); local
1615 // Split Mask operand
1617 if (Mask
2026 SDValue Mask = N->getOperand(0); local
2245 SDValue Mask = MGT->getMask(); local
2313 SDValue Mask = N->getMask(); local
2372 SDValue Mask = N->getMask(); local
3718 SDValue Mask = N->getMask(); local
3743 SDValue Mask = N->getMask(); local
3846 SDValue Mask; local
3963 SDValue Mask; local
4517 SDValue Mask = MST->getMask(); local
4557 SDValue Mask = MG->getMask(); local
4576 SDValue Mask = MSC->getMask(); local
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/freebsd-12-stable/contrib/llvm-project/clang/lib/AST/Interp/
H A DDescriptor.cpp274 unsigned Mask = 1ull << static_cast<uint64_t>(I % PER_FIELD); local
275 if (!(data()[Bucket] & Mask)) {
276 data()[Bucket] |= Mask;
284 unsigned Mask = 1ull << static_cast<uint64_t>(I % PER_FIELD); local
285 return data()[Bucket] & Mask;
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFormMemoryClauses.cpp234 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(MO.getSubReg());
235 if ((Conflict->second.second & Mask).any())
273 LaneBitmask Mask = Register::isVirtualRegister(Reg) local
281 Map[Reg] = std::make_pair(State, Mask);
284 Loc->second.second |= Mask;
H A DGCNDPPCombine.cpp88 int64_t Mask = -1) const;
344 int64_t Value, int64_t Mask) const {
350 return (Imm->getImm() & Mask) == Value;
496 const int64_t Mask = ~(SISrcMods::ABS | SISrcMods::NEG); local
497 if (!hasNoImmOrEqual(OrigMI, AMDGPU::OpName::src0_modifiers, 0, Mask) ||
498 !hasNoImmOrEqual(OrigMI, AMDGPU::OpName::src1_modifiers, 0, Mask) ||
H A DSIMachineFunctionInfo.h124 Optional<unsigned> Mask; member in struct:llvm::yaml::SIArgument
135 Mask = Other.Mask;
144 Mask = Other.Mask;
181 YamlIO.mapOptional("mask", A.Mask);
/freebsd-12-stable/contrib/llvm-project/llvm/lib/IR/
H A DAutoUpgrade.cpp958 static Value *getX86MaskVec(IRBuilder<> &Builder, Value *Mask, argument
961 cast<IntegerType>(Mask->getType())->getBitWidth());
962 Mask = Builder.CreateBitCast(Mask, MaskTy);
970 Mask = Builder.CreateShuffleVector(Mask, Mask,
975 return Mask;
978 static Value *EmitX86Select(IRBuilder<> &Builder, Value *Mask, argument
981 if (const auto *C = dyn_cast<Constant>(Mask))
989 EmitX86ScalarSelect(IRBuilder< &Builder, Value *Mask, Value *Op0, Value *Op1) argument
1007 UpgradeX86ALIGNIntrinsics(IRBuilder< &Builder, Value *Op0, Value *Op1, Value *Shift, Value *Passthru, Value *Mask, bool IsVALIGN) argument
1128 Value *Mask = CI.getOperand(3); local
1155 Value *Mask = CI.getOperand(3); local
1228 Value *Mask = CI.getOperand(NumArgs - 1); local
1234 UpgradeMaskedStore(IRBuilder< &Builder, Value *Ptr, Value *Data, Value *Mask, bool Aligned) argument
1254 UpgradeMaskedLoad(IRBuilder< &Builder, Value *Ptr, Value *Passthru, Value *Mask, bool Aligned) argument
1317 Constant *Mask = ConstantInt::get(Ty, 0xffffffff); local
1331 ApplyX86MaskOn1BitsVec(IRBuilder< &Builder, Value *Vec, Value *Mask) argument
1377 Value *Mask = CI.getArgOperand(CI.getNumArgOperands() - 1); local
1395 Value* Mask = CI.getArgOperand(3); local
1410 Value *Mask = getX86MaskVec(Builder, Op, NumElts); local
1775 Value *Mask = Builder.CreateAnd(CI->getArgOperand(2), Builder.getInt8(1)); local
1849 Value *Mask = CI->getArgOperand(2); local
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Support/Unix/
H A DMemory.inc239 const intptr_t Mask = ~(LineSize - 1);
240 const intptr_t StartLine = ((intptr_t) Addr) & Mask;
241 const intptr_t EndLine = ((intptr_t) Addr + Len + LineSize - 1) & Mask;
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/Utils/
H A DX86ShuffleDecode.cpp18 // Vector Mask Decoding
387 SmallVectorImpl<int> &Mask) {
393 Mask.push_back(i);
395 Mask.push_back(IsAnyExtend ? SM_SentinelUndef : SM_SentinelZero);
407 SmallVectorImpl<int> &Mask) {
410 Mask.push_back(NumElts);
412 Mask.push_back(IsLoad ? static_cast<int>(SM_SentinelZero) : i);
532 // Bits[2:1] - (Per Lane) PD Shuffle Mask.
533 // Bits[2:0] - (Per Lane) PS Shuffle Mask.
385 DecodeZeroExtendMask(unsigned SrcScalarBits, unsigned DstScalarBits, unsigned NumDstElts, bool IsAnyExtend, SmallVectorImpl<int> &Mask) argument
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/ADT/
H A DPointerEmbeddedInt.h47 Mask = static_cast<uintptr_t>(-1) << Bits
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DConstantFolding.h125 Constant *Mask);
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/
H A DDwarfExpression.cpp94 void DwarfExpression::addAnd(unsigned Mask) { argument
95 emitConstu(Mask);
527 uint64_t Mask = (1ULL << (uint64_t)SubRegisterSizeInBits) - 1ULL; local
528 addAnd(Mask);
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.h43 const uint32_t **Mask) const;
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp908 unsigned Mask = Op.getImm() & 0xf;
910 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
912 switch (Mask) {
932 if (Mask) {
934 if (Mask & 8)
936 if (Mask & 4)
938 if (Mask & 2)
940 if (Mask
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/freebsd-12-stable/contrib/llvm-project/llvm/tools/llvm-dwp/
H A Dllvm-dwp.cpp304 uint64_t Mask = Buckets.size() - 1; local
308 auto H = S & Mask;
309 auto HP = ((S >> 32) & Mask) | 1;
313 H = (H + HP) & Mask;
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp297 int64_t Mask = 0xffff; local
299 Offset = OldOffset & Mask;
301 Mask >>= 1;
302 assert(Mask && "One offset must be OK");
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DLowerMatrixIntrinsics.cpp252 Constant *Mask = createSequentialMask(Builder, MaskStart, SI.NumRows, 0); local
253 Value *V = Builder.CreateShuffleVector(MatrixVal, Undef, Mask, "split");
621 Constant *Mask = createSequentialMask(Builder, I, NumElts, 0); local
622 return Builder.CreateShuffleVector(Col, Undef, Mask, "block");
642 SmallVector<Constant *, 16> Mask; local
645 Mask.push_back(Builder.getInt32(i));
649 Mask.push_back(Builder.getInt32(i - I + VecNumElts));
652 Mask.push_back(Builder.getInt32(i));
654 Value *MaskVal = ConstantVector::get(Mask);
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveRegMatrix.cpp86 LaneBitmask Mask = (*Units).second; local
88 if ((S.LaneMask & Mask).any()) {
H A DMachineFunction.cpp482 uint32_t *Mask = Allocator.Allocate<uint32_t>(Size); local
483 memset(Mask, 0, Size * sizeof(Mask[0]));
484 return Mask;
487 ArrayRef<int> MachineFunction::allocateShuffleMask(ArrayRef<int> Mask) { argument
488 int* AllocMask = Allocator.Allocate<int>(Mask.size());
489 copy(Mask, AllocMask);
490 return {AllocMask, Mask.size()};
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCSymbol.h420 void modifyFlags(uint32_t Value, uint32_t Mask) const {
422 Flags = (Flags & ~Mask) | Value;
H A DSubtargetFeature.h86 uint64_t Mask = uint64_t(1) << (I % 64); local
87 return (Bits[I / 64] & Mask) != 0;
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DRDFCopy.cpp124 if ((RC.LaneMask & RR.Mask) == RC.LaneMask)
127 if (RR.Mask == TRI.getSubRegIndexLaneMask(S.getSubRegIndex()))

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