Searched refs:Mask (Results 126 - 150 of 334) sorted by relevance

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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CallLowering.cpp818 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CalleeCC); local
820 TRI->UpdateCustomCallPreservedMask(MF, &Mask);
821 MIB.addRegMask(Mask);
975 const uint32_t *Mask = TRI->getCallPreservedMask(MF, Info.CallConv); local
977 TRI->UpdateCustomCallPreservedMask(MF, &Mask);
978 MIB.addRegMask(Mask);
H A DAArch64RegisterInfo.cpp155 const uint32_t **Mask) const {
158 memcpy(UpdatedMask, *Mask, sizeof(UpdatedMask[0]) * RegMaskSize);
171 *Mask = UpdatedMask;
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AddressingModes.h225 uint64_t Mask = (1ULL << Size) - 1; local
227 if ((Imm & Mask) != ((Imm >> Size) & Mask)) {
235 uint64_t Mask = ((uint64_t)-1LL) >> (64 - Size); local
236 Imm &= Mask;
243 Imm |= ~Mask;
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp89 unsigned Mask = MBBI->getOperand(1).getImm(); local
95 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
661 unsigned Mask = (1 << NumBits) - 1;
662 if ((unsigned)Offset <= Mask * Scale &&
687 ImmedOffset = ImmedOffset & Mask;
700 Offset &= ~(Mask*Scale);
/freebsd-12-stable/sys/dev/rp/
H A Drp.c478 Interrupt Mask Register if the CHANINT_EN flag is set. This allows
491 Byte_t Mask; /* Interrupt Mask Register */ local
504 Mask = rp_readch1(ChP,_INT_MASK) | rp_sBitMapSetTbl[ChP->ChanNum];
505 rp_writech1(ChP,_INT_MASK,Mask);
530 Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
536 Byte_t Mask; /* Interrupt Mask Register */ local
546 Mask = rp_readch1(ChP,_INT_MASK) & rp_sBitMapClrTbl[ChP->ChanNum];
547 rp_writech1(ChP,_INT_MASK,Mask);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp631 ConstantSDNode *Mask, SDNode *&NodeToMask);
4704 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), local
4706 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) {
4707 ADDC |= Mask;
4891 ConstantSDNode *Mask,
4902 (Mask->getAPIntValue() & C->getAPIntValue()) != C->getAPIntValue())
4914 if (isAndLoadExtLoad(Mask, Load, Load->getValueType(0), ExtVT) &&
4932 unsigned ActiveBits = Mask->getAPIntValue().countTrailingOnes();
4947 if (!SearchForAndLoads(Op.getNode(), Loads, NodesWithConsts, Mask,
4978 auto *Mask local
4888 SearchForAndLoads(SDNode *N, SmallVectorImpl<LoadSDNode*> &Loads, SmallPtrSetImpl<SDNode*> &NodesWithConsts, ConstantSDNode *Mask, SDNode *&NodeToMask) argument
5144 SDValue Mask = DAG.getConstant( local
5226 APInt Mask = ~N1C->getAPIntValue(); local
5968 stripConstantMask(SelectionDAG &DAG, SDValue Op, SDValue &Mask) argument
5978 matchRotateHalf(SelectionDAG &DAG, SDValue Op, SDValue &Shift, SDValue &Mask) argument
6012 extractShiftForRotate(SelectionDAG &DAG, SDValue OppShift, SDValue ExtractFrom, SDValue &Mask, const SDLoc &DL) argument
6350 SDValue Mask = AllOnes; local
7643 APInt Mask = APInt::getHighBitsSet(OpSizeInBits, OpSizeInBits - c1); local
7982 SDValue Mask = DAG.getConstant(APInt::getLowBitsSet(InnerShiftSize, local
7996 SDValue Mask = local
8019 APInt Mask = APInt::getLowBitsSet(OpSizeInBits, OpSizeInBits - ShiftAmt); local
8755 SDValue Mask = MSC->getMask(); local
8768 SDValue Mask = MST->getMask(); local
8785 SDValue Mask = MGT->getMask(); local
8797 SDValue Mask = MLD->getMask(); local
9405 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); local
9712 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); local
9981 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); local
10036 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); local
10197 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); local
10408 const APInt &Mask = AndC->getAPIntValue(); local
10889 APInt Mask = local
14255 auto Mask = local
15046 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), local
15177 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, local
16742 ArrayRef<int> Mask = SVN->getMask(); local
18045 SmallVector<int, 8> Mask; local
18724 ArrayRef<int> Mask = SVN->getMask(); local
18952 ArrayRef<int> Mask = SVN->getMask(); local
19049 getShuffleMaskIndexOfOneElementFromOp0IntoOp1(ArrayRef<int> Mask) argument
19077 ArrayRef<int> Mask = Shuf->getMask(); local
19437 SmallVector<int, 4> Mask; local
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H A DLegalizeVectorOps.cpp1005 SDValue Mask = Node->getOperand(0); local
1009 assert(VT.isVector() && !Mask.getValueType().isVector()
1029 Mask = DAG.getSelect(DL, BitTy, Mask,
1035 Mask = DAG.getSplatBuildVector(MaskTy, DL, Mask);
1045 SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes);
1047 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask);
1255 SDValue Mask = Node->getOperand(0); local
1259 EVT VT = Mask
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineOperand.cpp544 for (const auto &Mask : BitMasks) {
546 if ((BitMask & Mask.first) == Mask.first) {
550 OS << Mask.second;
552 BitMask &= ~(Mask.first);
933 ArrayRef<int> Mask = getShuffleMask(); local
935 for (int Elt : Mask) {
H A DStackMaps.cpp256 StackMaps::parseRegisterLiveOutMask(const uint32_t *Mask) const {
257 assert(Mask && "No register mask specified");
263 if ((Mask[Reg / 32] >> (Reg % 32)) & 1)
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelDAGToDAG.cpp55 unsigned Mask = MI.getOperand(1).getImm(); local
59 if (Mask & 1)
62 if (Mask & 2)
65 if (Mask & 4)
68 if (Mask & 8)
71 if (Mask & 16)
74 if (Mask & 32)
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp399 APInt &Mask) const override;
414 APInt &Mask) const {
418 assert(Mask.getBitWidth() == NumDefs + NumImplicitDefs &&
448 Mask.clearAllBits();
452 Mask.setBit(I);
458 Mask.setBit(NumDefs + I);
461 return Mask.getBoolValue();
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h1507 // The memory for Mask is owned by the SelectionDAG's OperandAllocator, and
1509 const int *Mask; member in class:llvm::ShuffleVectorSDNode
1515 : SDNode(ISD::VECTOR_SHUFFLE, Order, dl, getSDVTList(VT)), Mask(M) {}
1520 return makeArrayRef(Mask, VT.getVectorNumElements());
1525 return Mask[Idx];
1528 bool isSplat() const { return isSplatMask(Mask, getValueType(0)); }
1534 if (Mask[i] >= 0)
1535 return Mask[i];
1542 static bool isSplatMask(const int *Mask, EVT VT);
1546 static void commuteMask(MutableArrayRef<int> Mask) { argument
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp813 int Mask = -cast<ConstantSDNode>(A.getNode())->getSExtValue(); local
814 assert(isPowerOf2_32(-Mask));
816 SDValue M = CurDAG->getTargetConstant(Mask, dl, MVT::i32);
1076 // Transform: (load ch (add x (and (srl y c) Mask)))
1079 // Mask = 00..0 111..1 0.0
1101 // T0 must match: (and T1 Mask)
1124 uint32_t Mask = MN->getZExtValue(); local
1126 uint32_t TZ = countTrailingZeros(Mask);
1127 uint32_t M1 = countTrailingOnes(Mask >> TZ);
1128 uint32_t LZ = countLeadingZeros(Mask);
1534 uint64_t Mask = (1 << NumBits) - 1; local
1552 uint64_t Mask = (1 << NumBits) - 1; local
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/freebsd-12-stable/contrib/llvm-project/openmp/runtime/src/
H A Dkmp.h39 // Mask for determining index into stack block
590 KAFFINITY Mask; member in struct:GROUP_AFFINITY
656 class Mask { class in class:KMPAffinity
662 virtual ~Mask() {}
672 virtual void copy(const Mask *src) {}
674 virtual void bitwise_and(const Mask *rhs) {}
676 virtual void bitwise_or(const Mask *rhs) {}
701 virtual Mask *allocate_mask() { return nullptr; }
702 virtual void deallocate_mask(Mask *m) {}
703 virtual Mask *allocate_mask_arra
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp709 unsigned Mask = 0; local
714 Mask |= 1ULL << I;
720 OpVals.push_back(Mask);
1623 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv); local
1624 assert(Mask && "Missing call preserved mask for calling convention");
1625 Ops.push_back(DAG.getRegisterMask(Mask));
2031 uint64_t Mask = (1 << NumBits) - 1; local
2035 if (uint64_t(SignedValue) + (uint64_t(1) << (NumBits - 1)) > Mask)
2040 Value &= Mask;
2056 if (Value > Mask)
2285 getTestUnderMaskCond(unsigned BitSize, unsigned CCMask, uint64_t Mask, uint64_t CmpVal, unsigned ICmpType) argument
2388 ConstantSDNode *Mask = nullptr; local
3578 uint64_t Mask = cast<ConstantSDNode>(HighOp.getOperand(1))->getZExtValue(); local
6460 unsigned Mask = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); local
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86MCInstLower.cpp1759 unsigned SrcOp2Idx, ArrayRef<int> Mask) {
1782 SmallVector<int, 8> ShuffleMask(Mask.begin(), Mask.end());
2301 SmallVector<int, 64> Mask; local
2302 DecodePSHUFBMask(C, Width, Mask);
2303 if (!Mask.empty())
2304 OutStreamer->AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask));
2373 SmallVector<int, 16> Mask; local
2374 DecodeVPERMILPMask(C, ElSize, Width, Mask);
2375 if (!Mask
1758 getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx, unsigned SrcOp2Idx, ArrayRef<int> Mask) argument
2404 SmallVector<int, 16> Mask; local
2421 SmallVector<int, 16> Mask; local
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H A DX86RegisterInfo.cpp611 void X86RegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
619 assert(!(Mask[X86::EFLAGS / 32] & (1U << (X86::EFLAGS % 32))) &&
624 Mask[Reg / 32] &= ~(1U << (Reg % 32));
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Demangle/
H A DMicrosoftDemangleNodes.cpp54 Qualifiers Mask, bool NeedSpace) {
55 if (!(Q & Mask))
61 outputSingleQualifier(OS, Mask);
53 outputQualifierIfPresent(OutputStream &OS, Qualifiers Q, Qualifiers Mask, bool NeedSpace) argument
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/IR/
H A DFunction.h182 unsigned Mask = 1 << IsMaterializableBit; local
183 setGlobalObjectSubClassData((~Mask & getGlobalObjectSubClassData()) |
184 (V ? Mask : 0u));
H A DNoFolder.h328 Constant *Mask) const {
329 return new ShuffleVectorInst(V1, V2, Mask);
/freebsd-12-stable/contrib/llvm-project/llvm/tools/llvm-readobj/
H A DARMEHABIPrinter.h33 uint8_t Mask; member in struct:llvm::ARM::EHABI::OpcodeDecoder::RingEntry
63 void PrintRegisters(uint32_t Mask, StringRef Prefix);
312 if ((Opcodes[OCI ^ 3] & RE.Mask) == RE.Value) {
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/ADT/
H A DAPInt.h151 // Mask out the high bits.
1438 WordType Mask = maskBit(BitPosition);
1440 U.VAL |= Mask;
1442 U.pVal[whichWord(BitPosition)] |= Mask;
1512 WordType Mask = ~maskBit(BitPosition);
1514 U.VAL &= Mask;
1516 U.pVal[whichWord(BitPosition)] &= Mask;
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DScalarEvolution.h345 maskFlags(SCEVWrapPredicate::IncrementWrapFlags Flags, int Mask) { argument
347 assert((Mask & IncrementNoWrapMask) == Mask && "Invalid mask value!");
349 return (SCEVWrapPredicate::IncrementWrapFlags)(Flags & Mask);
462 int Mask) {
463 return (SCEV::NoWrapFlags)(Flags & Mask);
461 maskFlags(SCEV::NoWrapFlags Flags, int Mask) argument
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DVPlan.h878 VPValue *Mask)
880 if (Mask)
881 User.addOperand(Mask);
898 // Mask is optional and therefore the last, currently 2nd operand.
991 /// control converges back from a Branch-on-Mask. The phi nodes are needed in
1001 /// nodes after merging back from a Branch-on-Mask.
1028 VPValue *Mask)
1030 if (Mask)
1031 User.addOperand(Mask);
1047 // Mask i
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/DebugInfo/MSF/
H A DMSFBuilder.cpp329 uint8_t Mask = uint8_t(IsFree) << I; local
330 ThisByte |= Mask;

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