/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 653 setTargetDAGCombine(ISD::MUL); 737 setOperationAction(ISD::MUL, MVT::v1i64, Expand); 773 // AArch64 doesn't have MUL.2d: 774 setOperationAction(ISD::MUL, MVT::v2i64, Expand); 776 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 777 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 778 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 2246 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS); 2288 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS); 2878 "unexpected type for custom-lowering ISD::MUL"); [all...] |
H A D | AArch64ISelDAGToDAG.cpp | 585 if (Op1.getOpcode() != ISD::MUL || 589 if (Op1.getOpcode() != ISD::MUL ||
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H A D | AArch64FastISel.cpp | 4691 return selectBinaryOp(I, ISD::MUL); 5019 /// MUL at all and ADD is lowered very inefficientily.
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 652 setOperationAction(ISD::MUL , VT, Expand); 754 setOperationAction(ISD::MUL, MVT::v4f32, Legal); 763 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 765 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 767 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 768 setOperationAction(ISD::MUL, MVT::v16i8, Custom); 821 setOperationAction(ISD::MUL, MVT::v2f64, Legal); 1171 setTargetDAGCombine(ISD::MUL); 3149 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32, 10504 case ISD::MUL [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorTypes.cpp | 133 case ISD::MUL: 908 case ISD::MUL: 2073 case ISD::VECREDUCE_MUL: CombineOpc = ISD::MUL; break; 2713 case ISD::MUL:
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H A D | LegalizeVectorOps.cpp | 368 case ISD::MUL:
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H A D | SelectionDAG.cpp | 2785 case ISD::MUL: { 3822 case ISD::MUL: { 4790 case ISD::MUL: return C1 * C2; 5193 case ISD::MUL: 5494 case ISD::MUL: 5743 Value = DAG.getNode(ISD::MUL, dl, IntVT, Value,
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H A D | SelectionDAGBuilder.cpp | 3967 IdxN = DAG.getNode(ISD::MUL, dl, 4003 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
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/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/TableGen/ |
H A D | Record.h | 803 enum BinaryOp : uint8_t { ADD, MUL, AND, OR, SHL, SRA, SRL, LISTCONCAT,
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 967 if (ROOTNode->getOperand(0).getOpcode() != ISD::MUL && 968 ROOTNode->getOperand(1).getOpcode() != ISD::MUL) 997 SDValue Mult = ROOTNode->getOperand(0).getOpcode() == ISD::MUL 1001 SDValue AddOperand = ROOTNode->getOperand(0).getOpcode() == ISD::MUL
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H A D | MipsFastISel.cpp | 2129 // We treat the MUL instruction in a special way because it clobbers 2135 if (MachineInstOpcode == Mips::MUL) {
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 849 setOperationAction(ISD::MUL, MVT::v1i64, Expand); 851 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 852 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 853 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 1059 setOperationAction(ISD::MUL, MVT::i64, Expand); 1450 setTargetDAGCombine(ISD::MUL); 5339 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, dl, PTy)); 8574 "unexpected type for custom-lowering ISD::MUL"); 9342 case ISD::MUL: return LowerMUL(Op, DAG); 11301 if (Mul.getOpcode() != ISD::MUL) { [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | TargetLoweringBase.cpp | 1599 case Mul: return ISD::MUL;
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/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | TargetLowering.h | 2243 case ISD::MUL: 4047 /// Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes, 4051 /// \param LL Low bits of the LHS of the MUL. You can use this parameter 4053 /// \param LH High bits of the LHS of the MUL. See LL for meaning. 4054 /// \param RL Low bits of the RHS of the MUL. See LL for meaning 4055 /// \param RH High bits of the RHS of the MUL. See LL for meaning. 4063 /// Expand a MUL into two nodes. One that computes the high bits of 4066 /// \param LL Low bits of the LHS of the MUL. You can use this parameter 4068 /// \param LH High bits of the LHS of the MUL. See LL for meaning. 4069 /// \param RL Low bits of the RHS of the MUL [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.cpp | 164 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIISelLowering.cpp | 616 setOperationAction(ISD::MUL, MVT::v2i16, Legal); 645 setOperationAction(ISD::MUL, MVT::v4i16, Custom); 4094 case ISD::MUL: 9516 if ((LHS.getOpcode() == ISD::MUL || RHS.getOpcode() == ISD::MUL) 9520 if (LHS.getOpcode() != ISD::MUL)
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 358 setOperationAction(ISD::MUL, VT, Legal); 2621 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, Op0, Op1);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1650 setOperationAction(ISD::MUL, MVT::i32, Expand);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelDAGToDAG.cpp | 2040 case ISD::MUL: 4792 default: llvm_unreachable("Unknown MUL opcode!");
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