Searched refs:LIS (Results 26 - 50 of 88) sorted by relevance

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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.h64 LiveIntervals &LIS) const override;
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DModuloSchedule.h167 LiveIntervals &LIS; member in class:llvm::ModuloScheduleExpander
256 LiveIntervals &LIS, InstrChangesTy InstrChanges)
258 TII(ST.getInstrInfo()), LIS(LIS),
279 LiveIntervals *LIS; member in class:llvm::PeelingModuloScheduleExpander
310 LiveIntervals *LIS)
312 TII(ST.getInstrInfo()), LIS(LIS) {}
255 ModuloScheduleExpander(MachineFunction &MF, ModuloSchedule &S, LiveIntervals &LIS, InstrChangesTy InstrChanges) argument
309 PeelingModuloScheduleExpander(MachineFunction &MF, ModuloSchedule &S, LiveIntervals *LIS) argument
H A DLiveRegMatrix.h42 LiveIntervals *LIS; member in class:llvm::LiveRegMatrix
H A DLiveRangeEdit.h73 LiveIntervals &LIS; member in class:llvm::LiveRangeEdit
142 : Parent(parent), NewRegs(newRegs), MRI(MF.getRegInfo()), LIS(lis),
236 /// to erase it from LIS.
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIWholeQuadMode.cpp154 LiveIntervals *LIS; member in class:__anon5034::SIWholeQuadMode
288 LiveRange &LR = LIS->getRegUnit(*RegUnit);
289 const VNInfo *Value = LR.Query(LIS->getInstructionIndex(MI)).valueIn();
298 markInstruction(*LIS->getInstructionFromIndex(Value->def), Flag,
570 LIS->InsertMachineInstrInMaps(*Save);
571 LIS->InsertMachineInstrInMaps(*Restore);
572 LIS->createAndComputeVirtRegInterval(SaveReg);
586 LiveRange &LR = LIS->getRegUnit(*MCRegUnitIterator(AMDGPU::SCC, TRI));
588 SlotIndex FirstIdx = First != MBBE ? LIS->getInstructionIndex(*First)
589 : LIS
[all...]
H A DGCNSchedStrategy.cpp338 if (LIS) {
352 if (!LIS)
415 LIS->handleMove(*MI, true);
426 SlotIndex SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();
427 RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx, MI);
430 RegOpers.detectDeadDefs(*MI, *LIS);
444 GCNDownwardRPTracker RPTracker(*LIS);
450 GCNDownwardRPTracker RPTracker(*LIS);
457 SlotIndexes *Ind = LIS->getSlotIndexes();
480 assert(isEqual(getLiveRegsBefore(*NonDbgMI, *LIS), LR
[all...]
H A DGCNNSAReassign.cpp80 LiveIntervals *LIS; member in class:__anon4989::GCNNSAReassign
211 if (!LIS->hasInterval(Reg))
233 LIS = &getAnalysis<LiveIntervals>();
281 LiveInterval *LI = &LIS->getInterval(Reg);
311 return LIS->getInstructionIndex(*C.first) < I;
314 LIS->getInstructionIndex(*I->first) < MaxInd; ++I) {
H A DSIFormMemoryClauses.cpp317 LiveIntervals *LIS = &getAnalysis<LiveIntervals>(); local
318 SlotIndexes *Ind = LIS->getSlotIndexes();
338 GCNDownwardRPTracker RPT(*LIS);
395 LIS->removeInterval(Reg);
396 LIS->createAndComputeVirtRegInterval(Reg);
403 LIS->removeInterval(Reg);
404 LIS->createAndComputeVirtRegInterval(Reg);
H A DSIRegisterInfo.h242 LiveIntervals &LIS) const override;
288 LiveIntervals *LIS) const;
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegisterPressure.cpp237 static const LiveRange *getLiveRange(const LiveIntervals &LIS, unsigned Reg) { argument
239 return &LIS.getInterval(Reg);
240 return LIS.getCachedRegUnit(Reg);
245 LIS = nullptr;
281 LIS = lis;
314 return LIS->getMBBEndIdx(MBB);
315 return LIS->getInstructionIndex(*IdxPos).getRegSlot();
421 static LaneBitmask getLanesWithProperty(const LiveIntervals &LIS, argument
426 const LiveInterval &LI = LIS.getInterval(RegUnit);
440 const LiveRange *LR = LIS
449 getLiveLanesAt(const LiveIntervals &LIS, const MachineRegisterInfo &MRI, bool TrackLaneMasks, unsigned RegUnit, SlotIndex Pos) argument
[all...]
H A DRegAllocBasic.cpp145 LiveInterval &LI = LIS->getInterval(VirtReg);
164 LiveInterval &LI = LIS->getInterval(VirtReg);
238 LiveRangeEdit LRE(&Spill, SplitVRegs, *MF, *LIS, VRM, this, &DeadRemats);
297 LiveRangeEdit LRE(&VirtReg, SplitVRegs, *MF, *LIS, VRM, this, &DeadRemats);
314 calculateSpillWeightsAndHints(*LIS, *MF, VRM,
H A DSplitKit.h51 const LiveIntervals &LIS; member in class:llvm::InsertPointAnalysis
82 SlotIndex Res = LIS.getMBBStartIdx(&MBB);
86 Res = LIS.getInstructionIndex(*MII);
99 const LiveIntervals &LIS; member in class:llvm::SplitAnalysis
260 LiveIntervals &LIS; member in class:llvm::SplitEditor
H A DLiveRegMatrix.cpp57 LIS = &getAnalysis<LiveIntervals>();
155 LIS->checkRegMaskInterference(VirtReg, RegMaskUsable);
172 const LiveRange &UnitRange = LIS->getRegUnit(Unit);
173 return Range.overlaps(UnitRange, CP, *LIS->getSlotIndexes());
H A DRegAllocBase.h67 LiveIntervals *LIS = nullptr; member in class:llvm::RegAllocBase
H A DRegAllocGreedy.cpp637 LiveInterval &LI = LIS->getInterval(VirtReg);
656 LiveInterval &LI = LIS->getInterval(VirtReg);
716 LIS->intervalIsInOneMBB(*LI)) {
752 LiveInterval *LI = &LIS->getInterval(~CurQueue.top().second);
879 bool IsLocal = LIS->intervalIsInOneMBB(VirtReg);
949 if (!MaxCost.isMax() && IsLocal && LIS->intervalIsInOneMBB(*Intf) &&
1201 !LIS->getInstructionFromIndex(BI.LastInstr)->isImplicitDef())
1286 SlotIndex::isEarlierInstr(LIS->getInstructionIndex(MBB->instr_front()),
1497 getCheapestEvicteeWeight(Order, LIS->getInterval(Evictee),
1512 if (!LIS
[all...]
H A DModuloSchedule.cpp185 LIS.RemoveMachineInstrFromMaps(I);
337 LiveIntervals &LIS) {
346 if (!LIS.hasInterval(ToReg))
347 LIS.createEmptyInterval(ToReg);
538 replaceRegUsesAfterLoop(Def, NewReg, BB, MRI, LIS);
578 replaceRegUsesAfterLoop(Def, NewReg, BB, MRI, LIS);
596 replaceRegUsesAfterLoop(Def, VRMap[CurStageNum][LoopVal], BB, MRI, LIS);
692 replaceRegUsesAfterLoop(Def, NewReg, BB, MRI, LIS);
755 LIS.RemoveMachineInstrFromMaps(*MI);
770 LIS
334 replaceRegUsesAfterLoop(unsigned FromReg, unsigned ToReg, MachineBasicBlock *MBB, MachineRegisterInfo &MRI, LiveIntervals &LIS) argument
1217 EliminateDeadPhis(MachineBasicBlock *MBB, MachineRegisterInfo &MRI, LiveIntervals *LIS, bool KeepSingleSrcPhi = false) argument
1252 LiveIntervals *LIS; member in class:__anon4606::KernelRewriter
1280 KernelRewriter(MachineLoop &L, ModuloSchedule &S, LiveIntervals *LIS) argument
2147 LiveIntervals &LIS = getAnalysis<LiveIntervals>(); local
[all...]
H A DVirtRegMap.cpp181 LiveIntervals *LIS; member in class:__anon4672::VirtRegRewriter
241 LIS = &getAnalysis<LiveIntervals>();
248 LIS->addKillFlags(VRM);
317 LiveInterval &LI = LIS->getInterval(VirtReg);
318 if (LI.empty() || LIS->intervalIsInOneMBB(LI))
356 const LiveInterval &LI = LIS->getInterval(Reg);
358 SlotIndex BaseIndex = LIS->getInstructionIndex(MI);
472 SlotIndex MIIndex = LIS->getInstructionIndex(MI);
476 const LiveRange &UnitRange = LIS->getRegUnit(*Unit);
H A DInterferenceCache.h62 /// LIS - Used for accessing register mask interference maps.
63 LiveIntervals *LIS = nullptr; member in class:llvm::InterferenceCache::Entry
108 LIS = lis;
H A DInterferenceCache.cpp119 RegUnits.back().Fixed = &LIS->getRegUnit(*Units);
193 RegMaskSlots = LIS->getRegMaskSlotsInBlock(MBBNum);
194 RegMaskBits = LIS->getRegMaskBitsInBlock(MBBNum);
H A DLiveIntervals.cpp956 LiveIntervals& LIS; member in class:LiveIntervals::HMEditor
965 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI, argument
968 : LIS(LIS), MRI(MRI), TRI(TRI), OldIdx(OldIdx), NewIdx(NewIdx),
977 return &LIS.getRegUnit(Unit);
978 return LIS.getCachedRegUnit(Unit);
1004 LiveInterval &LI = LIS.getInterval(Reg);
1074 if (MachineInstr *KillMI = LIS.getInstructionFromIndex(OldIdxIn->end))
1375 if (MachineInstr *KillMI = LIS.getInstructionFromIndex(NewIdx))
1398 llvm::lower_bound(LIS
[all...]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCTLSDynamicCall.cpp46 LiveIntervals *LIS; member in struct:__anon5316::PPCTLSDynamicCall
145 LIS->repairIntervalsInRange(&MBB, First, Last, OrigRegs);
155 LIS = &getAnalysis<LiveIntervals>();
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.h65 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override;
H A DHexagonRegisterInfo.cpp243 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const {
259 const SlotIndexes &Indexes = *LIS.getSlotIndexes();
275 return !any_of(LIS.getInterval(DstReg), HasCall) &&
276 !any_of(LIS.getInterval(SrcReg), HasCall);
284 return any_of(LIS.getInterval(LargeReg), HasCall) ||
285 !any_of(LIS.getInterval(SmallReg), HasCall);
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.h93 LiveIntervals &LIS) const override;
H A DSystemZRegisterInfo.cpp346 LiveIntervals &LIS) const {
361 LiveInterval &IntGR128 = LIS.getInterval(GR128Reg);
362 LiveInterval &IntGRNar = LIS.getInterval(GRNarReg);
367 LIS.getInstructionFromIndex(IntGR128.beginIndex());
369 LIS.getInstructionFromIndex(IntGRNar.beginIndex());
370 MachineInstr *LastMI_GR128 = LIS.getInstructionFromIndex(IntGR128.endIndex());
371 MachineInstr *LastMI_GRNar = LIS.getInstructionFromIndex(IntGRNar.endIndex());

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