Searched refs:Def (Results 101 - 125 of 172) sorted by relevance

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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Transforms/Coroutines/
H A DCoroFrame.cpp290 Value *Def = nullptr; member in class:__anon5513::Spill
295 Spill(Value *Def, llvm::User *U) : Def(Def), User(cast<Instruction>(U)) {} argument
297 Value *def() const { return Def; }
317 // Note that there may be more than one record with the same value of Def in
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DRDFGraph.cpp93 case NodeAttrs::Def: OS << 'd'; break;
161 case NodeAttrs::Def:
797 if (NA.Addr->getKind() == NodeAttrs::Def) {
826 NodeAddr<DefNode*> DA = newNode(NodeAttrs::Ref | NodeAttrs::Def | Flags);
833 NodeAddr<DefNode*> DA = newNode(NodeAttrs::Ref | NodeAttrs::Def | Flags);
1529 if (M.Addr->getKind() != NodeAttrs::Def)
1622 assert(Kind == NodeAttrs::Def || Kind == NodeAttrs::Use);
1626 assert(Kind != NodeAttrs::Def || !Defs.count(RR));
1636 else if (Kind == NodeAttrs::Def)
H A DMachineCSE.cpp647 MachineInstr *Def = MRI->getUniqueVRegDef(NewReg); local
648 assert(Def != nullptr && "CSEd register has no unique definition?");
649 Def->clearRegisterDeads(NewReg);
H A DRDFLiveness.cpp227 return TA.Addr->getKind() == NodeAttrs::Def &&
454 if (!DFG.IsRef<NodeAttrs::Def>(R))
670 NodeList Ds = PA.Addr->members_if(DFG.IsRef<NodeAttrs::Def>, DFG);
H A DInlineSpiller.cpp917 /// Check if \p Def fully defines a VReg with an undefined value.
920 static bool isFullUndefDef(const MachineInstr &Def) { argument
921 if (!Def.isImplicitDef())
923 assert(Def.getNumOperands() == 1 &&
925 // We can say that the VReg defined by Def is undef, only if it is
926 // fully defined by Def. Otherwise, some of the lanes may not be
928 return !Def.getOperand(0).getSubReg();
H A DTwoAddressInstructionPass.cpp368 MachineInstr *Def = getSingleDef(TmpReg, MBB, MRI); local
369 if (!Def || !Def->isCopy())
372 TmpReg = Def->getOperand(1).getReg();
/freebsd-12-stable/contrib/llvm-project/clang/lib/AST/
H A DDeclBase.cpp1197 if (auto *Def = OID->getDefinition())
1198 return Def;
1203 if (auto *Def = OPD->getDefinition())
1204 return Def;
1220 if (TagDecl *Def = Tag->getDefinition())
1221 return Def;
H A DType.cpp2115 bool Type::isIncompleteType(NamedDecl **Def) const {
2116 if (Def)
2117 *Def = nullptr;
2127 if (Def)
2128 *Def = EnumD;
2135 if (Def)
2136 *Def = Rec;
2145 ->isIncompleteType(Def);
2173 ->isIncompleteType(Def);
2178 if (Def)
[all...]
H A DDecl.cpp550 const FunctionDecl *Def = nullptr; local
556 FD->hasBody(Def) && Def->isInlined() && !Def->hasAttr<GNUInlineAttr>();
2252 VarDecl *Def = nullptr; local
2261 Def = I;
2264 return Def;
2471 if (auto *Def = D->getDefinition())
2472 return Def;
/freebsd-12-stable/contrib/llvm-project/clang/lib/Sema/
H A DSemaTemplate.cpp1763 if (TagDecl *Def = PrevRecordDecl->getDefinition()) {
1767 if (SkipBody && !hasVisibleDefinition(Def, &Hidden)) {
1769 SkipBody->Previous = Def;
1777 Diag(Def->getLocation(), diag::note_previous_definition);
8290 RecordDecl *Def = Specialization->getDefinition(); local
8292 if (Def && SkipBody && !hasVisibleDefinition(Def, &Hidden)) {
8294 SkipBody->Previous = Def;
8296 } else if (Def) {
8299 Diag(Def
9253 dllExportImportClassTemplateSpecialization( Sema &S, ClassTemplateSpecializationDecl *Def) argument
9492 ClassTemplateSpecializationDecl *Def local
9656 CXXRecordDecl *Def local
[all...]
H A DSemaDecl.cpp1969 ObjCInterfaceDecl *Def = dyn_cast_or_null<ObjCInterfaceDecl>(IDecl); local
1971 if (Def && Def->getDefinition())
1972 Def = Def->getDefinition();
1973 return Def;
2617 const VarDecl *Def = VD->getDefinition(); local
2618 if (Def)
2619 return Def;
2640 const NamedDecl *Def local
11766 VarDecl *Def; local
15572 TagDecl *Def; local
16153 NamedDecl *Def; local
[all...]
H A DSemaType.cpp7825 auto *Def = Var->getDefinition(); local
7826 if (!Def) {
7831 Def = Var->getDefinition();
7838 if (Var->getPointOfInstantiation().isInvalid() && Def) {
7849 if (Def) {
7850 DRE->setDecl(Def);
7851 QualType T = Def->getType();
8096 NamedDecl *Def = nullptr; local
8097 bool Incomplete = T->isIncompleteType(&Def);
8101 if (Def
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H A DSemaLambda.cpp1634 NamedDecl *Def; local
1635 FieldType->isIncompleteType(&Def);
1636 if (Def && Def->isInvalidDecl()) {
H A DSemaLookup.cpp1597 bool Sema::hasVisibleMergedDefinition(NamedDecl *Def) { argument
1598 for (const Module *Merged : Context.getModulesWithMergedDefinition(Def))
1604 bool Sema::hasMergedDefinitionInCurrentModule(NamedDecl *Def) { argument
1605 for (const Module *Merged : Context.getModulesWithMergedDefinition(Def))
5329 NamedDecl *Def = getDefinitionToImport(Decl);
5330 if (!Def)
5331 Def = Decl;
5333 Module *Owner = getOwningModule(Def);
5338 auto Merged = Context.getModulesWithMergedDefinition(Def);
5341 diagnoseMissingImport(Loc, Def, De
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/freebsd-12-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenSchedule.cpp299 for (const Record *Def : Fn.getDefinitions()) {
300 RecVec Classes = Def->getValueAsListOfDefs("Classes");
330 for (const Record *Def : Fn.getDefinitions()) {
331 RecVec Classes = Def->getValueAsListOfDefs("Classes");
332 const Record *SchedModel = Def->getValueAsDef("SchedModel");
723 unsigned CodeGenSchedModels::getSchedRWIdx(const Record *Def, argument
727 RWVec, [Def](const CodeGenSchedRW &RW) { return RW.TheDef == Def; });
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp137 MachineInstr *Def = MRI.getVRegDef(Reg); local
138 assert(Def && "Operand not defined");
139 switch (Def->getOpcode()) {
144 for (const MachineOperand &BuildVecMO : Def->uses())
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSILowerI1Copies.cpp771 static void instrDefsUsesSCC(const MachineInstr &MI, bool &Def, bool &Use) {
772 Def = false;
780 Def = true;
H A DSIInsertWaitcnts.cpp268 bool Def) const;
467 unsigned OpNo, bool Def) const {
470 (Def && !Op.isDef()) || TRI->isAGPR(*MRI, Op.getReg()))
1039 MachineOperand &Def = MI.getOperand(I); local
1044 if (TRI->isVGPR(MRIA, Def.getReg())) {
H A DSIRegisterInfo.cpp1888 MachineInstr *Def = LIS->getInstructionFromIndex(DefIdx); local
1890 if (!Def || !MDT.dominates(Def, &Use))
1893 assert(Def->modifiesRegister(Reg, this));
1895 return Def;
H A DSIPeepholeSDWA.cpp526 for (const MachineOperand &Def : MRI->def_operands(Op.getReg())) {
527 if (!isSameReg(Op, Def))
530 const MachineInstr *DefInst = Def.getParent();
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGISel.cpp580 MachineInstr *Def = RegInfo->getVRegDef(Reg); local
581 if (Def) {
582 MachineBasicBlock::iterator InsertPos = Def;
584 Def->getParent()->insert(std::next(InsertPos), MI);
595 MachineInstr *Def = RegInfo->getVRegDef(LDI->second); local
596 MachineBasicBlock::iterator InsertPos = Def;
606 // Def is never a terminator here, so it is ok to increment InsertPos.
2120 /// findNonImmUse - Return true if "Def" is a predecessor of "Root" via a path
2122 static bool findNonImmUse(SDNode *Root, SDNode *Def, SDNode *ImmedUse, argument
2126 // Only check if we have non-immediate uses of Def
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/TableGen/
H A DRecord.cpp1596 : TypedInit(IK_DefInit, D->getType()), Def(D) {}
1610 if (const RecordVal *RV = Def->getValue(FieldName))
1616 return Def->getName();
1653 if (!Def) {
1692 Def = DefInit::get(NewRec);
1695 return Def;
1720 if (Def)
1721 return Def;
1769 Record *Def = DI->getDef();
1770 if (Def
[all...]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DIndVarSimplify.cpp236 /// viable location is found: it may happen if User is a PHI and Def only comes
238 static Instruction *getInsertPointForUses(Instruction *User, Value *Def, argument
246 if (PHI->getIncomingValue(i) != Def)
262 // If we have skipped all inputs, it means that Def only comes to Phi from
267 auto *DefI = dyn_cast<Instruction>(Def);
1032 Optional<ConstantRange> getPostIncRangeInfo(Value *Def, argument
1034 DefUserPair Key(Def, UseI);
1044 void updatePostIncRangeInfo(Value *Def, Instruction *UseI, ConstantRange R) { argument
1045 DefUserPair Key(Def, UseI);
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86SpeculativeLoadHardening.cpp1678 for (MachineOperand &Def : MI.defs())
1679 if (Def.isReg())
1680 LoadDepRegs.set(Def.getReg());
1761 for (MachineOperand &Def : MI.defs())
1762 if (Def.isReg())
1763 LoadDepRegs.set(Def.getReg());
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp262 static bool isHighLatencyCPSR(MachineInstr *Def) { argument
263 switch(Def->getOpcode()) {

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