Searched refs:f16 (Results 51 - 75 of 76) sorted by relevance

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/freebsd-12-stable/crypto/openssl/crypto/sha/asm/
H A Dsha1-sparcv9a.pl87 "%f8", "%f9","%f10","%f11","%f12","%f13","%f14","%f15","%f16");
473 fpadd32 $VK_00_19,@X[0],%f16
481 std %f16,[$Xfer+0]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp263 return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::f16);
392 return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::f16);
435 return isSCSrcB16() || isLiteralImm(MVT::f16);
473 return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::f16);
505 return isVCSrcF16() || isLiteralImm(MVT::f16);
529 return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::f16);
553 return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::f16);
577 return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::f16);
601 return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::f16);
625 return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::f16);
[all...]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp718 addRegisterClass(MVT::f16, &ARM::HPRRegClass);
721 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
723 setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
724 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal);
994 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
995 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f16, Custom);
1009 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
1014 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
1015 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
1307 setOperationAction(ISD::SETCC, MVT::f16, Expan
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/freebsd-12-stable/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
H A DRegisterInfos_mips64.h305 DEFINE_FPR(f16, nullptr, dwarf_f16_mips64, dwarf_f16_mips64,
/freebsd-12-stable/crypto/openssl/crypto/bn/asm/
H A Dia64-mont.pl378 ni0=f16; ni1=f17; ni2=f18; ni3=f19; ni4=f20; ni5=f21; ni6=f22; ni7=f23;
398 stf.spill [sp]=f16,-16
844 { .mmi; ldf.fill f16=[r16],64
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeFloatTypes.cpp479 // There's only a libcall for f16 -> f32, so proceed in two stages. Also, it's
480 // entirely possible for both f16 and f32 to be legal, so use the fully
482 if (Op.getValueType() == MVT::f16 && N->getValueType(0) != MVT::f32) {
831 EVT FloatRVT = N->getOpcode() == ISD::FP_TO_FP16 ? MVT::f16 : RVT;
1938 if (OpVT == MVT::f16) {
1940 } else if (RetVT == MVT::f16) {
2157 // Bitcast from i16 to f16: convert the i16 to a f32 value instead.
H A DLegalizeDAG.cpp314 while (SVT != MVT::f32 && SVT != MVT::f16) {
902 if (SrcVT.getScalarType() == MVT::f16) {
3214 // the result. Since "f16 -> f32" is much more commonly available, give
4137 RTLIB::getFPROUND(Node->getOperand(0).getValueType(), MVT::f16);
H A DSelectionDAG.cpp1384 EltVT == MVT::f16) {
4407 if (VT == MVT::f16 && C->getValueType(0) == MVT::i16)
4498 if (VT == MVT::i16 && C->getValueType(0) == MVT::f16)
H A DSelectionDAGBuilder.cpp6286 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
6294 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
H A DTargetLowering.cpp1904 if ((OpVTLegal || i32Legal) && VT.isSimple() && SrcVT != MVT::f16 &&
/freebsd-12-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenTarget.cpp71 case MVT::f16: return "MVT::f16";
H A DIntrinsicEmitter.cpp267 case MVT::f16: return Sig.push_back(IIT_F16);
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp177 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
178 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
196 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
197 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
2684 .Cases("{f16}", "{fa6}", {RISCV::F16_F, RISCV::F16_D})
/freebsd-12-stable/crypto/openssl/crypto/
H A Dsparccpuid.S106 fmovs %f0,%f16
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp104 // WebAssembly currently has no builtin f16 support.
107 setLoadExtAction(ISD::EXTLOAD, T, MVT::f16, Expand);
108 setTruncStoreAction(T, MVT::f16, Expand);
H A DWebAssemblyFastISel.cpp134 case MVT::f16:
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp2882 if (SrcVT == MVT::f128 || SrcVT == MVT::f16)
2910 if (DestVT == MVT::f16)
2996 else if ((VT >= MVT::f16 && VT <= MVT::f64) || VT.is64BitVector() ||
3034 } else if (VT == MVT::f16) {
H A DAArch64ISelDAGToDAG.cpp1241 } else if (VT == MVT::f16) {
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp320 // for f32, f16
323 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
326 // Set LoadExtAction for f16 vectors to Expand
328 MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements());
333 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
334 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
451 // Lower f16 conversion operations into library calls
/freebsd-12-stable/sys/sparc64/sparc64/
H A Dexception.S1216 ldda [PCB_REG + PCB_UFP + (1 * 64)] %asi, %f16
1267 ldda [PCB_REG + PCB_KFP + (1 * 64)] %asi, %f16
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h1408 case MVT::f16: return APFloat::IEEEhalf();
/freebsd-12-stable/contrib/gdb/gdb/
H A Drs6000-tdep.c2184 /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp171 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Legal);
172 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Legal);
173 setTruncStoreAction(MVT::f64, MVT::f16, Legal);
174 setTruncStoreAction(MVT::f32, MVT::f16, Legal);
176 // No extending loads from f16 or HW conversions back and forth.
177 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
180 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
183 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
184 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
15451 // false. Examples: f16, f8
[all...]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp916 // Hack around using a legal type if f16 is illegal.
2119 // using the conversion from f16.
2127 // converted from f16 (in which case fmad isn't legal).
2579 assert(Src.getValueType() == MVT::f16);
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp378 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
379 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
380 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
381 setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f16, Expand);
382 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
383 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
384 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
385 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
824 // EXTLOAD for MVT::f16 vectors is not legal because f16 vector
[all...]

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