Lines Matching refs:f16
718 addRegisterClass(MVT::f16, &ARM::HPRRegClass);
721 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
723 setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
724 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal);
994 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
995 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f16, Custom);
1009 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
1014 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
1015 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
1307 setOperationAction(ISD::SETCC, MVT::f16, Expand);
1308 setOperationAction(ISD::SELECT, MVT::f16, Custom);
1309 setOperationAction(ISD::SELECT_CC, MVT::f16, Custom);
1317 setOperationAction(ISD::BR_CC, MVT::f16, Custom);
1346 // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
1352 // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
1359 setOperationAction(ISD::STRICT_FSETCC, MVT::f16, Custom);
1360 setOperationAction(ISD::STRICT_FSETCCS, MVT::f16, Custom);
1405 setOperationAction(ISD::FREM, MVT::f16, Promote);
1406 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand);
1407 setOperationAction(ISD::FSIN, MVT::f16, Promote);
1408 setOperationAction(ISD::FCOS, MVT::f16, Promote);
1409 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
1410 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
1411 setOperationAction(ISD::FPOW, MVT::f16, Promote);
1412 setOperationAction(ISD::FEXP, MVT::f16, Promote);
1413 setOperationAction(ISD::FEXP2, MVT::f16, Promote);
1414 setOperationAction(ISD::FLOG, MVT::f16, Promote);
1415 setOperationAction(ISD::FLOG10, MVT::f16, Promote);
1416 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
1418 setOperationAction(ISD::FROUND, MVT::f16, Legal);
1424 setOperationAction(ISD::FMINIMUM, MVT::f16, Legal);
1425 setOperationAction(ISD::FMAXIMUM, MVT::f16, Legal);
2793 // t11 f16 = fadd ...
2799 // that produces the f16 value, t11 in this case.
2867 ReturnF16 ? MVT::f16 : VA.getLocVT()));
4088 if (RegVT == MVT::f16)
4911 if (VT == MVT::f16)
5034 if (Subtarget->hasFPARMv8Base() && (TrueVal.getValueType() == MVT::f16 ||
5058 // match CMPFPw0 instead of CMPFP, though we don't do this for f16 because we
5059 // must use VSEL (limited condition codes), due to not having conditional f16
5062 !(isFloatingPointZero(RHS) && TrueVal.getValueType() != MVT::f16) &&
5063 (TrueVal.getValueType() == MVT::f16 ||
5730 // t18: f16 = ARMISD::VMOVhr t5
5740 SDValue Copy = DAG.getNode(ISD::CopyFromReg, SDLoc(Op), MVT::f16, Ops);
5745 if (SrcVT == MVT::i16 && DstVT == MVT::f16) {
5752 // t8: f16 = bitcast t7 <~~~~ N
5756 MVT::f16, Op.getOperand(0));
5762 if (SrcVT == MVT::f16 && DstVT == MVT::i16) {
5766 // t11: f16 = fadd t8, t10
7300 assert(FVT == MVT::f32 || FVT == MVT::f16);
8178 // INSERT_VECTOR_ELT doesn't want f16 operands promoting to f32,
14922 // combiner rewrite fneg into xors and some other instructions. For f16 and
14927 case MVT::f16:
15089 case MVT::f16:
15153 case MVT::f16:
16411 MVT SrcVT = (Sz == 16 ? MVT::f16 : MVT::f32);
16520 if (VT == MVT::f16 && Subtarget->hasFullFP16())
16997 // Ensure the vector doesn't have f16 elements. Even though we could do an
16998 // i16 vldN, we can't hold the f16 vectors and will end up converting via