Searched refs:Subtarget (Results 26 - 50 of 112) sorted by relevance

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/freebsd-11.0-release/contrib/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp227 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) {
234 if (Subtarget.hasMips32r6())
287 if (Subtarget.isGP64bit()) {
302 if (!Subtarget.isGP64bit()) {
309 if (Subtarget.isGP64bit())
335 if (Subtarget.hasCnMips()) {
353 if (!Subtarget.hasMips32r2())
356 if (!Subtarget.hasMips64r2())
394 if (!Subtarget.isGP64bit()) {
401 if (!Subtarget
470 performDivRemCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
580 performSELECTCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
659 performCMovFPCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
686 performANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
728 performORCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
784 performADDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
2357 const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>( local
[all...]
H A DMipsAsmPrinter.h97 const MipsSubtarget *Subtarget; member in class:llvm::MipsAsmPrinter
114 (Subtarget->inMips16Mode() && Subtarget->useConstantIslands());
H A DMipsISelDAGToDAG.h35 : SelectionDAGISel(TM), Subtarget(nullptr) {}
49 const MipsSubtarget *Subtarget; member in class:llvm::MipsDAGToDAGISel
H A DMipsTargetObjectFile.cpp88 const MipsSubtarget &Subtarget = local
92 if (!Subtarget.useSmallSection())
H A DMipsAsmPrinter.cpp61 Subtarget = &MF.getSubtarget<MipsSubtarget>();
68 if (Subtarget->inMips16Mode())
82 if (Subtarget->isTargetNaCl())
103 if (Subtarget->hasMips64r6()) {
107 } else if (Subtarget->hasMips32r6()) {
111 } else if (Subtarget->inMicroMipsMode())
122 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
200 if (I->isPseudo() && !Subtarget->inMips16Mode()
326 if (Subtarget->isTargetNaCl())
329 if (Subtarget
[all...]
H A DMipsSEISelDAGToDAG.cpp40 Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
41 if (Subtarget->inMips16Mode())
138 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
245 if (Subtarget->isGP64bit()) {
256 if (Subtarget->isGP64bit()) {
483 if (!Subtarget->hasMSA())
496 MinSizeInBits, !Subtarget->isLittle()))
720 unsigned Opc = Subtarget->isGP64bit() ? Mips::DSUBu : Mips::SUBu;
726 if (Subtarget->hasDSP()) // Select DSP instructions, ADDSC and ADDWC.
729 unsigned Opc = Subtarget
[all...]
H A DMipsSEISelLowering.cpp44 if (Subtarget.isGP64bit())
47 if (Subtarget.hasDSP() || Subtarget.hasMSA()) {
59 if (Subtarget.hasDSP()) {
83 if (Subtarget.hasDSPR2())
86 if (Subtarget.hasMSA()) {
102 if (!Subtarget.useSoftFloat()) {
106 if (!Subtarget.isSingleFloat()) {
107 if (Subtarget.isFP64bit())
119 if (Subtarget
528 performADDECombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
548 performANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
663 performORCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
783 performSUBECombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
848 performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty, SelectionDAG &DAG, const MipsSubtarget &Subtarget) argument
873 performSHLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
896 performSRACombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
942 performSRLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
1040 performXORCombine(SDNode *N, SelectionDAG &DAG, const MipsSubtarget &Subtarget) argument
[all...]
H A DMipsSEFrameLowering.cpp75 const MipsSubtarget &Subtarget; member in class:__anon2939::ExpandPseudo
83 Subtarget(static_cast<const MipsSubtarget &>(MF.getSubtarget())),
84 TII(*static_cast<const MipsSEInstrInfo *>(Subtarget.getInstrInfo())),
85 RegInfo(*Subtarget.getRegisterInfo()) {}
283 if ((Subtarget.isABI_FPXX() && !Subtarget.hasMTHC1()) ||
284 (FP64 && !Subtarget.useOddSPReg())) {
292 assert(Subtarget.isGP64bit() || Subtarget.hasMTHC1() ||
293 !Subtarget
[all...]
H A DMipsCCState.cpp59 const MipsSubtarget &Subtarget) {
61 if (Subtarget.inMips16HardFloat()) {
58 getSpecialCallingConvForCallee(const SDNode *Callee, const MipsSubtarget &Subtarget) argument
/freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp59 : TargetLowering(TM), Subtarget(STI) {
66 bool isPPC64 = Subtarget.isPPC64();
71 if (!Subtarget.useSoftFloat()) {
100 if (Subtarget.useCRBits()) {
103 if (isPPC64 || Subtarget.hasFPCVT()) {
177 if (!Subtarget.hasFSQRT() &&
178 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
179 Subtarget.hasFRE()))
182 if (!Subtarget.hasFSQRT() &&
183 !(TM.Options.UnsafeFPMath && Subtarget
1197 const PPCSubtarget& Subtarget = local
1955 GetLabelAccessInfo(const TargetMachine &TM, const PPCSubtarget &Subtarget, unsigned &HiOpFlags, unsigned &LoOpFlags, const GlobalValue *GV = nullptr) argument
4101 PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, SDValue &Chain, SDValue CallSeqStart, SDLoc dl, int SPDiff, bool isTailCall, bool IsPatchPoint, bool hasNest, SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass, SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys, ImmutableCallSite *CS, const PPCSubtarget &Subtarget) argument
[all...]
H A DPPCAsmPrinter.cpp71 const PPCSubtarget *Subtarget; member in class:__anon2970::PPCAsmPrinter
102 Subtarget = &MF.getSubtarget<PPCSubtarget>();
173 if (!Subtarget->isDarwin())
289 if (!Subtarget->isDarwin())
394 int TOCSaveOffset = Subtarget->isELFv2ABI() ? 24 : 40;
403 if (!Subtarget->isELFv2ABI()) {
464 ((Subtarget->isPPC64() && MI->getOperand(0).getReg() == PPC::X3) ||
465 (!Subtarget->isPPC64() && MI->getOperand(0).getReg() == PPC::R3)) &&
468 ((Subtarget->isPPC64() && MI->getOperand(1).getReg() == PPC::X3) ||
469 (!Subtarget
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/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/
H A DARMInstrInfo.cpp96 const ARMSubtarget &Subtarget = MF.getSubtarget<ARMSubtarget>(); local
98 if (!Subtarget.useMovt(MF)) {
114 if (!Subtarget.GVIsIndirectSymbol(GV, RM)) {
H A DARMSelectionDAGInfo.cpp30 const ARMSubtarget &Subtarget = local
32 const ARMTargetLowering *TLI = Subtarget.getTargetLowering();
139 const ARMSubtarget &Subtarget = local
152 if (!AlwaysInline && SizeVal > Subtarget.getMaxInlineSizeThreshold())
163 const unsigned MaxLoadsInLDM = Subtarget.isThumb1Only() ? 4 : 6;
H A DARMBaseInstrInfo.cpp97 Subtarget(STI) {
122 if (Subtarget.isThumb2() || Subtarget.hasVFP2())
662 const ARMSubtarget &Subtarget) const {
663 unsigned Opc = Subtarget.isThumb()
664 ? (Subtarget.isMClass() ? ARM::t2MRS_M : ARM::t2MRS_AR)
672 if (Subtarget.isMClass())
683 const ARMSubtarget &Subtarget) const {
684 unsigned Opc = Subtarget.isThumb()
685 ? (Subtarget
3462 adjustDefLatency(const ARMSubtarget &Subtarget, const MachineInstr *DefMI, const MCInstrDesc *DefMCID, unsigned DefAlign) argument
[all...]
H A DARMAsmPrinter.cpp92 (Subtarget->isTargetELF()
106 Subtarget = &MF.getSubtarget<ARMSubtarget>();
139 if (Subtarget->isTargetCOFF()) {
544 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI()))
559 const ARMSubtarget *Subtarget) {
563 if (Subtarget->hasV8Ops())
565 else if (Subtarget->hasV7Ops()) {
566 if (Subtarget->isMClass() && Subtarget
558 getArchForCPU(StringRef CPU, const ARMSubtarget *Subtarget) argument
[all...]
H A DARMISelDAGToDAG.cpp64 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
66 const ARMSubtarget *Subtarget; member in class:__anon2774::ARMDAGToDAGISel
74 Subtarget = &MF.getSubtarget<ARMSubtarget>();
340 if (!Subtarget->hasV6T2Ops())
343 bool isThumb2 = Subtarget->isThumb();
432 if (!Subtarget->isCortexA7() && !Subtarget->isCortexA8() &&
433 !Subtarget->isCortexA9() && !Subtarget->isSwift())
474 if (!Subtarget
3464 getMClassRegisterMask(StringRef Reg, StringRef Flags, bool IsRead, const ARMSubtarget *Subtarget) argument
[all...]
H A DARMFastISel.cpp77 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
79 const ARMSubtarget *Subtarget; member in class:__anon2769::final
94 Subtarget(
97 TM(funcInfo.MF->getTarget()), TII(*Subtarget->getInstrInfo()),
98 TLI(*Subtarget->getTargetLowering()) {
489 if (!Subtarget->hasVFP2()) return false;
517 if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) {
529 if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) {
546 if (Subtarget->useMovt(*FuncInfo.MF))
584 bool IsIndirect = Subtarget
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H A DARMTargetMachine.h35 ARMSubtarget Subtarget; member in class:llvm::ARMBaseTargetMachine
46 const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; }
/freebsd-11.0-release/contrib/llvm/lib/Target/Sparc/
H A DDelaySlotFiller.cpp45 const SparcSubtarget *Subtarget; member in struct:__anon2997::Filler
57 Subtarget = &F.getSubtarget<SparcSubtarget>();
110 Subtarget = &MBB.getParent()->getSubtarget<SparcSubtarget>();
111 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
127 if (!Subtarget->isV9() &&
190 slot->setDesc(Subtarget->getInstrInfo()->get(SP::RET));
332 for (MCRegAliasIterator AI(Reg, Subtarget->getRegisterInfo(), true);
485 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
H A DSparcInstrInfo.h41 const SparcSubtarget& Subtarget; member in class:llvm::SparcInstrInfo
/freebsd-11.0-release/contrib/llvm/lib/Target/X86/
H A DX86AsmPrinter.h29 const X86Subtarget *Subtarget; member in class:llvm::X86AsmPrinter
98 const X86Subtarget &getSubtarget() const { return *Subtarget; }
/freebsd-11.0-release/contrib/llvm/lib/Target/XCore/
H A DXCoreTargetMachine.cpp34 Subtarget(TT, CPU, FS, *this) {
/freebsd-11.0-release/contrib/llvm/lib/Target/BPF/
H A DBPFTargetMachine.cpp47 Subtarget(TT, CPU, FS, *this) {
/freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp42 // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
44 const AMDGPUSubtarget *Subtarget; member in class:__anon2721::AMDGPUDAGToDAGISel
162 Subtarget = &static_cast<const AMDGPUSubtarget &>(MF.getSubtarget());
187 Subtarget->getInstrInfo()->get(N->getMachineOpcode());
195 return Subtarget->getRegisterInfo()->getRegClass(RegClass);
200 Subtarget->getRegisterInfo()->getRegClass(RCID);
204 return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC,
265 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
325 Subtarget
[all...]
/freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.h130 const AArch64Subtarget &Subtarget = static_cast<const AArch64Subtarget &>( local
132 unsigned SlotAlign = Subtarget.isTargetDarwin() ? 1 : 8;

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