/freebsd-11.0-release/sys/crypto/sha2/ |
H A D | sha256c.c | 105 #define ROTR(x, n) ((x >> n) | (x << (32 - n))) macro 106 #define S0(x) (ROTR(x, 2) ^ ROTR(x, 13) ^ ROTR(x, 22)) 107 #define S1(x) (ROTR(x, 6) ^ ROTR(x, 11) ^ ROTR(x, 25)) 108 #define s0(x) (ROTR(x, 7) ^ ROTR(x, 18) ^ SHR(x, 3)) 109 #define s1(x) (ROTR( [all...] |
H A D | sha512c.c | 132 #define ROTR(x, n) ((x >> n) | (x << (64 - n))) macro 133 #define S0(x) (ROTR(x, 28) ^ ROTR(x, 34) ^ ROTR(x, 39)) 134 #define S1(x) (ROTR(x, 14) ^ ROTR(x, 18) ^ ROTR(x, 41)) 135 #define s0(x) (ROTR(x, 1) ^ ROTR(x, 8) ^ SHR(x, 7)) 136 #define s1(x) (ROTR( [all...] |
/freebsd-11.0-release/crypto/openssh/ |
H A D | blocks.c | 41 #define ROTR(x,c) (((x) >> (c)) | ((x) << (64 - (c)))) macro 45 #define Sigma0(x) (ROTR(x,28) ^ ROTR(x,34) ^ ROTR(x,39)) 46 #define Sigma1(x) (ROTR(x,14) ^ ROTR(x,18) ^ ROTR(x,41)) 47 #define sigma0(x) (ROTR(x, 1) ^ ROTR(x, 8) ^ SHR(x,7)) 48 #define sigma1(x) (ROTR( [all...] |
/freebsd-11.0-release/crypto/openssl/crypto/sha/asm/ |
H A D | sha512-mips.pl | 90 $ROTR="drotr"; 105 $ROTR="rotr"; 176 $ROTR $tmp0,$e,@Sigma1[0] 178 $ROTR $tmp1,$e,@Sigma1[1] 180 $ROTR $h,$e,@Sigma1[2] 182 $ROTR $tmp1,$a,@Sigma0[0] 186 $ROTR $h,$a,@Sigma0[1] 190 $ROTR $tmp1,$a,@Sigma0[2] 249 $ROTR $tmp0,@X[1],@sigma0[1] 252 $ROTR [all...] |
H A D | sha512-ia64.pl | 441 _rotr r10=$t1,$Sigma1[0] } // ROTR(e,14) 447 _rotr r11=$t1,$Sigma1[1] } // ROTR(e,41) 474 _rotr r10=$t1,$Sigma1[0] } // ROTR(e,14) 476 _rotr r11=$t1,$Sigma1[1] };; // ROTR(e,18) 481 _rotr r11=$t1,$Sigma1[2] } // ROTR(e,41) 486 _rotr r8=$t0,$Sigma0[0] } // ROTR(a,28) 488 _rotr r9=$t0,$Sigma0[1] };; // ROTR(a,34) 491 _rotr r9=$t0,$Sigma0[2] };; // ROTR(a,39) 509 _rotr r8=X[15-1],$sigma0[0] } // ROTR(s0,1) 513 _rotr r9=X[15-1],$sigma0[1] } // ROTR(s [all...] |
H A D | sha512-armv4.pl | 92 @ Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41)) 147 @ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39)) 326 @ sigma0(x) (ROTR((x),1) ^ ROTR((x),8) ^ ((x)>>7)) 343 @ sigma1(x) (ROTR((x),19) ^ ROTR(( [all...] |
/freebsd-11.0-release/crypto/openssl/crypto/sha/ |
H A D | sha512.c | 323 # define ROTR(a,n) ({ SHA_LONG64 ret; \ macro 353 # define ROTR(a,n) ({ SHA_LONG64 ret; \ macro 358 # define ROTR(a,n) ({ SHA_LONG64 ret; \ macro 373 # define ROTR(a,n) _rotr64((a),n) macro 402 # ifndef ROTR 403 # define ROTR(x,s) (((x)>>s) | (x)<<(64-s)) macro 405 # define Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39)) 406 # define Sigma1(x) (ROTR(( [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMSelectionDAGInfo.h | 29 case ISD::ROTR: return ARM_AM::ror; 30 //case ISD::ROTL: // Only if imm -> turn into ROTR.
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/freebsd-11.0-release/contrib/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 336 SHL, SRA, SRL, ROTL, ROTR, enumerator in enum:llvm::ISD::NodeType
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/freebsd-11.0-release/contrib/llvm/lib/Target/Mips/ |
H A D | Mips16ISelLowering.cpp | 147 setOperationAction(ISD::ROTR, MVT::i32, Expand); 148 setOperationAction(ISD::ROTR, MVT::i64, Expand);
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H A D | MipsFastISel.cpp | 1369 emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16);
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H A D | MipsISelLowering.cpp | 354 setOperationAction(ISD::ROTR, MVT::i32, Expand); 357 setOperationAction(ISD::ROTR, MVT::i64, Expand);
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/freebsd-11.0-release/contrib/llvm/lib/Target/X86/ |
H A D | X86IntrinsicsInfo.h | 1306 X86_INTRINSIC_DATA(avx512_mask_prorv_d_128, INTR_TYPE_2OP_MASK, ISD::ROTR, 0), 1307 X86_INTRINSIC_DATA(avx512_mask_prorv_d_256, INTR_TYPE_2OP_MASK, ISD::ROTR, 0), 1308 X86_INTRINSIC_DATA(avx512_mask_prorv_d_512, INTR_TYPE_2OP_MASK, ISD::ROTR, 0), 1309 X86_INTRINSIC_DATA(avx512_mask_prorv_q_128, INTR_TYPE_2OP_MASK, ISD::ROTR, 0), 1310 X86_INTRINSIC_DATA(avx512_mask_prorv_q_256, INTR_TYPE_2OP_MASK, ISD::ROTR, 0), 1311 X86_INTRINSIC_DATA(avx512_mask_prorv_q_512, INTR_TYPE_2OP_MASK, ISD::ROTR, 0),
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/freebsd-11.0-release/contrib/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 176 setOperationAction(ISD::ROTR, MVT::i64, Legal); 179 setOperationAction(ISD::ROTR, MVT::i64, Expand); 183 setOperationAction(ISD::ROTR, MVT::i32, Legal); 186 setOperationAction(ISD::ROTR, MVT::i32, Expand); 190 setOperationAction(ISD::ROTR, MVT::i16, Expand); 192 setOperationAction(ISD::ROTR, MVT::i8, Expand);
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/freebsd-11.0-release/contrib/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 98 setOperationAction(ISD::ROTR, MVT::i8, Expand); 100 setOperationAction(ISD::ROTR, MVT::i16, Expand);
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/freebsd-11.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGDumper.cpp | 195 case ISD::ROTR: return "rotr";
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H A D | LegalizeVectorOps.cpp | 283 case ISD::ROTR:
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H A D | SelectionDAG.cpp | 2625 case ISD::ROTR: 2630 if (Op.getOpcode() == ISD::ROTR) 3228 case ISD::ROTR: return std::make_pair(C1.rotr(C2), true); 3539 case ISD::ROTR: 6999 case ISD::ROTR:
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H A D | LegalizeIntegerTypes.cpp | 920 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break; 2679 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
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/freebsd-11.0-release/contrib/llvm/lib/Target/BPF/ |
H A D | BPFISelLowering.cpp | 132 setOperationAction(ISD::ROTR, MVT::i64, Expand);
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/freebsd-11.0-release/contrib/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.cpp | 151 {ISD::BSWAP, ISD::ROTL, ISD::ROTR, ISD::SMUL_LOHI, ISD::UMUL_LOHI,
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/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 1691 ISD::SDIVREM, ISD::UDIVREM, ISD::ROTL, ISD::ROTR, 1753 ISD::AND, ISD::OR, ISD::XOR, ISD::ROTL, ISD::ROTR,
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/freebsd-11.0-release/contrib/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 112 setOperationAction(ISD::ROTR , MVT::i32, Expand);
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/freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 264 // The hardware supports 32-bit ROTR, but not ROTL. 267 setOperationAction(ISD::ROTR, MVT::i64, Expand); 314 setOperationAction(ISD::ROTR, VT, Expand);
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/freebsd-11.0-release/contrib/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1582 setOperationAction(ISD::ROTR , MVT::i64, Expand); 1636 setOperationAction(ISD::ROTR , MVT::i32, Expand);
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