Searched refs:MI (Results 451 - 475 of 562) sorted by relevance

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/freebsd-11.0-release/contrib/llvm/lib/Target/X86/
H A DX86ISelLowering.h708 EmitInstrWithCustomInserter(MachineInstr *MI,
1106 MachineInstr *MI,
1120 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
1123 MachineBasicBlock *EmitLoweredCatchRet(MachineInstr *MI,
1126 MachineBasicBlock *EmitLoweredCatchPad(MachineInstr *MI,
1129 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
1132 MachineBasicBlock *EmitLoweredTLSAddr(MachineInstr *MI,
1135 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
1138 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
1141 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
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H A DX86ExpandPseudo.cpp67 MachineInstr &MI = *MBBI; local
68 unsigned Opcode = MI.getOpcode();
/freebsd-11.0-release/contrib/llvm/lib/CodeGen/AsmPrinter/
H A DDwarfDebug.cpp771 // Get .debug_loc entry for the instruction range starting at MI.
772 static DebugLocEntry::Value getDebugLocValue(const MachineInstr *MI) { argument
773 const DIExpression *Expr = MI->getDebugExpression();
775 assert(MI->getNumOperands() == 4);
776 if (MI->getOperand(0).isReg()) {
780 if (!MI->getOperand(1).isImm())
781 MLoc.set(MI->getOperand(0).getReg());
783 MLoc.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
786 if (MI
1031 getLabelBeforeInsn(const MachineInstr *MI) argument
1038 getLabelAfterInsn(const MachineInstr *MI) argument
1043 beginInstruction(const MachineInstr *MI) argument
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/freebsd-11.0-release/contrib/llvm/lib/Target/Mips/
H A DMips16InstrInfo.cpp46 unsigned Mips16InstrInfo::isLoadFromStackSlot(const MachineInstr *MI, argument
56 unsigned Mips16InstrInfo::isStoreToStackSlot(const MachineInstr *MI, argument
129 bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
130 MachineBasicBlock &MBB = *MI->getParent();
131 switch(MI->getDesc().getOpcode()) {
135 ExpandRetRA16(MBB, MI, Mips::JrcRa16);
139 MBB.erase(MI);
/freebsd-11.0-release/contrib/llvm/utils/TableGen/
H A DAsmMatcherEmitter.cpp627 const MatchableInfo* MI; member in struct:__anon4566::OperandMatchEntry
635 X.MI = mi;
1342 for (const auto &MI : Matchables) {
1347 for (unsigned i = 0, e = MI->AsmOperands.size(); i != e; ++i) {
1348 const MatchableInfo::AsmOperand &Op = MI->AsmOperands[i];
1359 OperandMatchInfo.push_back(OperandMatchEntry::create(MI.get(), CI,
2527 const MatchableInfo &II = *OMI.MI;
2669 for (const auto &MI : Info.Matchables)
2670 MI->dump();
2801 for (const auto &MI
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/freebsd-11.0-release/contrib/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp1193 MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI, argument
1197 DebugLoc dl = MI->getDebugLoc();
1202 switch (MI->getOpcode()) {
1242 RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
1256 unsigned ShiftAmtSrcReg = MI->getOperand(2).getReg();
1257 unsigned SrcReg = MI->getOperand(1).getReg();
1258 unsigned DstReg = MI->getOperand(0).getReg();
1294 MI->eraseFromParent(); // The pseudo instruction is gone now.
1299 MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, argument
1301 unsigned Opc = MI
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/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp411 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, argument
417 switch (MI.getOpcode()) {
432 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, argument
454 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
457 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
462 Result = decodeInstruction(DecoderTableVFP32, MI, Insn, Address, this, STI);
468 Result = decodeInstruction(DecoderTableVFPV832, MI, Insn, Address, this, STI);
475 decodeInstruction(DecoderTableNEONData32, MI, Insn, Address, this, STI);
480 if (!DecodePredicateOperand(MI, 0xE, Address, this))
485 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, Ins
541 tryAddingSymbolicOperand(uint64_t Address, int32_t Value, bool isBranch, uint64_t InstSize, MCInst &MI, const void *Decoder) argument
569 AddThumb1SBit(MCInst &MI, bool InITBlock) argument
688 getInstruction(MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, raw_ostream &OS, raw_ostream &CS) const argument
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/freebsd-11.0-release/contrib/llvm/tools/clang/lib/Basic/
H A DModule.cpp395 for (submodule_const_iterator MI = submodule_begin(), MIEnd = submodule_end();
396 MI != MIEnd; ++MI)
401 if (!(*MI)->IsInferred || (*MI)->IsFramework)
402 (*MI)->print(OS, Indent + 2);
/freebsd-11.0-release/contrib/llvm/tools/clang/include/clang/Lex/
H A DPreprocessor.h629 MacroInfo MI; member in struct:clang::Preprocessor::MacroInfoChain
638 MacroInfo MI; member in struct:clang::Preprocessor::DeserializedMacroInfoChain
872 DefMacroDirective *appendDefMacroDirective(IdentifierInfo *II, MacroInfo *MI, argument
874 DefMacroDirective *MD = AllocateDefMacroDirective(MI, Loc);
879 MacroInfo *MI) {
880 return appendDefMacroDirective(II, MI, MI->getDefinitionLoc());
1463 void DumpMacro(const MacroInfo &MI) const;
1693 DefMacroDirective *AllocateDefMacroDirective(MacroInfo *MI,
1713 /// Lex the rest of the arguments and the closing ), updating \p MI wit
878 appendDefMacroDirective(IdentifierInfo *II, MacroInfo *MI) argument
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/freebsd-11.0-release/contrib/llvm/lib/CodeGen/
H A DMachineInstrBundle.cpp53 MachineInstr *MI = &*MII; local
57 if (MI->isBundle()) {
66 MI->eraseFromParent();
272 // Remember each (MI, OpNo) that refers to Reg.
H A DMachineScheduler.cpp356 DEBUG(dbgs() << "Subtarget disables post-MI-sched.\n");
359 DEBUG(dbgs() << "Before post-MI-sched:\n"; mf.print(dbgs()));
388 static bool isSchedBoundary(MachineBasicBlock::iterator MI, argument
392 return MI->isCall() || TII->isSchedulingBoundary(MI, MBB, *MF);
463 DEBUG(dbgs() << "********** MI Scheduling **********\n");
633 MachineInstr *MI, MachineBasicBlock::iterator InsertPos) {
635 if (&*RegionBegin == MI)
639 BB->splice(InsertPos, BB, MI);
643 LIS->handleMove(MI, /*UpdateFlag
632 moveInstruction( MachineInstr *MI, MachineBasicBlock::iterator InsertPos) argument
700 MachineInstr *MI = SU->getInstr(); local
1229 MachineInstr *MI = SU->getInstr(); local
1411 HasDataDep(const TargetRegisterInfo &TRI, const MachineInstr &MI, const MachineInstr &Other) argument
2623 const MachineInstr *MI = SU->getInstr(); local
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H A DIfConversion.cpp1009 /// values defined in MI which are not live/used by MI.
1010 static void UpdatePredRedefs(MachineInstr *MI, LivePhysRegs &Redefs) { argument
1012 Redefs.stepForward(*MI, Clobbers);
1048 static void RemoveKills(MachineInstr &MI, const LivePhysRegs &DontKill) { argument
1049 for (MIBundleOperands O(&MI); O.isValid(); ++O) {
1526 static bool MaySpeculate(const MachineInstr *MI, argument
1529 if (!MI->isSafeToMove(nullptr, SawStore))
1532 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1533 const MachineOperand &MO = MI
1602 MachineInstr *MI = MF.CloneMachineInstr(I); local
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H A DTargetLoweringBase.cpp1094 TargetLoweringBase::emitPatchPoint(MachineInstr *MI, argument
1096 MachineFunction &MF = *MI->getParent()->getParent();
1111 // MI changes inside this loop as we grow operands.
1112 for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) {
1113 MachineOperand &MO = MI->getOperand(OperIdx);
1117 // foldMemoryOperand builds a new MI after replacing a single FI operand
1120 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
1124 MIB.addOperand(MI->getOperand(i));
1131 assert(MI
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/freebsd-11.0-release/contrib/llvm/include/llvm/Target/
H A DTargetSubtargetInfo.h109 const MachineInstr *MI,
177 /// \brief Enable use of alias analysis during code generation (during MI
108 resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const argument
/freebsd-11.0-release/contrib/llvm/include/llvm/Analysis/
H A DMemoryLocation.h89 static MemoryLocation getForDest(const MemIntrinsic *MI);
/freebsd-11.0-release/contrib/llvm/tools/lldb/tools/lldb-mi/
H A DMIDriverMgr.cpp69 MI::ModuleInit<CMICmnLog>(IDS_MI_INIT_ERR_LOG, bOk, errMsg);
70 MI::ModuleInit<CMICmnResources>(IDS_MI_INIT_ERR_RESOURCES, bOk, errMsg);
115 MI::ModuleShutdown<CMICmnResources>(IDE_MI_SHTDWN_ERR_RESOURCES, bOk, errMsg);
116 MI::ModuleShutdown<CMICmnLog>(IDS_MI_SHTDWN_ERR_LOG, bOk, errMsg);
433 // --executable is necessary to differentiate whither the MI Driver is being using
436 // executable if called from the command line. Using --executable tells the MI
462 // Print MI application path to the Log file
541 // Todo: Remove this output when MI is finished. It is temporary to persuade Eclipse plugin to work.
560 // Both '--help' and '--interpreter' means give help for MI only. Without
569 // This makes the assumption that there is at least one MI compatibl
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H A DMICmnLLDBDebugSessionInfo.h35 // Details: MI debug session object that holds debugging information between
36 // instances of MI commands executing their work and producing MI
42 class CMICmnLLDBDebugSessionInfo : public CMICmnBase, public MI::ISingleton<CMICmnLLDBDebugSessionInfo>
44 friend class MI::ISingleton<CMICmnLLDBDebugSessionInfo>;
80 bool m_bHaveArgOptionThreadGrp; // True = include MI field, false = do not include "thread-groups".
/freebsd-11.0-release/contrib/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp2979 SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, argument
2981 switch (MI->getOpcode()) {
2987 return expandSelectCC(MI, BB, SP::BCOND);
2992 return expandSelectCC(MI, BB, SP::FBCOND);
2995 return expandAtomicRMW(MI, BB, SP::ADDrr);
2997 return expandAtomicRMW(MI, BB, SP::ADDXrr);
2999 return expandAtomicRMW(MI, BB, SP::SUBrr);
3001 return expandAtomicRMW(MI, BB, SP::SUBXrr);
3003 return expandAtomicRMW(MI, BB, SP::ANDrr);
3005 return expandAtomicRMW(MI, B
3042 expandSelectCC(MachineInstr *MI, MachineBasicBlock *BB, unsigned BROpcode) const argument
3101 expandAtomicRMW(MachineInstr *MI, MachineBasicBlock *MBB, unsigned Opcode, unsigned CondCode) const argument
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/freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.h105 MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr * MI,
115 void AdjustInstrPostInstrSelection(MachineInstr *MI,
/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.h55 void addConstant(MCInst &MI, uint64_t Value, MCContext &Context);
105 unsigned getDuplexCandidateGroup(MCInst const &MI);
/freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h517 EmitInstrWithCustomInserter(MachineInstr *MI,
519 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
523 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI,
527 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
530 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
/freebsd-11.0-release/contrib/llvm/lib/Target/SystemZ/
H A DSystemZFrameLowering.cpp306 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII->get(Opcode), Reg) local
309 MI->getOperand(3).setIsDead();
517 MachineBasicBlock::iterator MI) const {
518 switch (MI->getOpcode()) {
523 MBB.erase(MI);
/freebsd-11.0-release/contrib/llvm/tools/llvm-ar/
H A Dllvm-ar.cpp469 auto MI =
474 if (MI == Members.end())
477 Pos = MI;
496 failIfError(sys::fs::status(*MI, Status), *MI);
/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp1340 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1342 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
7028 SetupEntryBlockForSjLj(MachineInstr *MI, MachineBasicBlock *MBB, argument
7031 DebugLoc dl = MI->getDebugLoc();
7067 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
7073 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2)
7077 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3)
7080 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12))
7094 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1)
7098 BuildMI(*MBB, MI, d
7142 EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const argument
7640 EmitStructByval(MachineInstr *MI, MachineBasicBlock *BB) const argument
7874 EmitLowered__chkstk(MachineInstr *MI, MachineBasicBlock *MBB) const argument
7940 EmitLowered__dbzchk(MachineInstr *MI, MachineBasicBlock *MBB) const argument
7966 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) const argument
8225 attachMEMCPYScratchRegs(const ARMSubtarget *Subtarget, MachineInstr *MI, const SDNode *Node) argument
8250 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const argument
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/freebsd-11.0-release/contrib/llvm/tools/clang/lib/Frontend/
H A DMultiplexConsumer.cpp36 void MacroRead(serialization::MacroID ID, MacroInfo *MI) override;
66 serialization::MacroID ID, MacroInfo *MI) {
68 Listener->MacroRead(ID, MI);
65 MacroRead( serialization::MacroID ID, MacroInfo *MI) argument

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