/freebsd-11.0-release/contrib/llvm/lib/CodeGen/ |
H A D | RegAllocBase.cpp | 115 MachineInstr *MI = nullptr; local 121 MI = TmpMI; 125 if (MI) 126 MI->emitError("inline assembly requires more registers than available");
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H A D | LiveVariables.cpp | 132 MachineInstr *MI) { 143 VRInfo.Kills.back() = MI; 174 VRInfo.Kills.push_back(MI); 182 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) { argument 187 VRInfo.Kills.push_back(MI); 231 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) { argument 276 PhysRegUse[*SubRegs] = MI; 311 bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *MI) { argument 397 } else if (LastRefOrPartRef == PhysRegDef[Reg] && LastRefOrPartRef != MI) { 443 void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI, argument 131 HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB, MachineInstr *MI) argument 486 UpdatePhysRegDefs(MachineInstr *MI, SmallVectorImpl<unsigned> &Defs) argument 500 runOnInstr(MachineInstr *MI, SmallVectorImpl<unsigned> &Defs) argument 577 MachineInstr *MI = I; local 690 removeVirtualRegistersKilled(MachineInstr *MI) argument [all...] |
H A D | CalcSpillWeights.cpp | 91 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def); 92 assert(MI && "Dead valno in interval"); 98 while (MI->isFullCopy()) { 100 if (MI->getOperand(0).getReg() != Reg) 104 Reg = MI->getOperand(1).getReg(); 119 MI = LIS.getInstructionFromIndex(VNI->def); 120 assert(MI && "Dead valno in interval"); 124 if (!TII.isTriviallyReMaterializable(MI, LIS.getAliasAnalysis()))
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H A D | SlotIndexes.cpp | 45 // Iterate over all MBBs, and within each MBB all MIs, keeping the MI 49 // is the same one pointed to by the MI iterator. This 185 MachineInstr *MI = (MBBI != MBB->end() && !pastStart) ? MBBI : nullptr; local 188 if (SlotMI == MI && !MBBIAtBegin) { 194 } else if (MI && mi2iMap.find(MI) == mi2iMap.end()) { 210 MachineInstr *MI = I; local 211 if (!MI->isDebugValue() && mi2iMap.find(MI) == mi2iMap.end()) 212 insertMachineInstrInMaps(MI); [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/Disassembler/ |
H A D | AArch64ExternalSymbolizer.h | 31 bool tryAddingSymbolicOperand(MCInst &MI, raw_ostream &CommentStream,
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/freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPURegisterInfo.h | 49 void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
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/freebsd-11.0-release/contrib/llvm/lib/Target/XCore/ |
H A D | XCoreMCInstLower.cpp | 107 void XCoreMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { argument 108 OutMI.setOpcode(MI->getOpcode()); 110 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 111 const MachineOperand &MO = MI->getOperand(i);
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H A D | XCoreFrameLowering.h | 36 MachineBasicBlock::iterator MI, 40 MachineBasicBlock::iterator MI,
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/freebsd-11.0-release/contrib/llvm/lib/Target/BPF/ |
H A D | BPFMCInstLower.h | 35 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
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/freebsd-11.0-release/contrib/llvm/lib/Target/Mips/ |
H A D | Mips16InstrInfo.h | 35 unsigned isLoadFromStackSlot(const MachineInstr *MI, 43 unsigned isStoreToStackSlot(const MachineInstr *MI, 47 MachineBasicBlock::iterator MI, DebugLoc DL, 65 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
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H A D | MipsInstrInfo.cpp | 51 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const 54 BuildMI(MBB, MI, DL, get(Mips::NOP)); 261 unsigned MipsInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 262 switch (MI->getOpcode()) { 264 return MI->getDesc().getSize(); 266 const MachineFunction *MF = MI->getParent()->getParent(); 267 const char *AsmStr = MI->getOperand(0).getSymbolName(); 273 return MI->getOperand(2).getImm();
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/freebsd-11.0-release/contrib/llvm/lib/Target/SystemZ/ |
H A D | SystemZMCInstLower.cpp | 95 void SystemZMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { argument 96 OutMI.setOpcode(MI->getOpcode()); 97 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) { 98 const MachineOperand &MO = MI->getOperand(I);
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H A D | SystemZMCInstLower.h | 32 // Lower MachineInstr MI to MCInst OutMI. 33 void lower(const MachineInstr *MI, MCInst &OutMI) const;
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/freebsd-11.0-release/contrib/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyMCInstLower.h | 42 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
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H A D | WebAssemblyRegisterInfo.h | 38 void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
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/freebsd-11.0-release/contrib/llvm/tools/lldb/tools/lldb-mi/ |
H A D | MICmnStreamStdin.cpp | 70 MI::ModuleInit<CMICmnLog>(IDS_MI_INIT_ERR_LOG, bOk, errMsg); 71 MI::ModuleInit<CMICmnResources>(IDS_MI_INIT_ERR_RESOURCES, bOk, errMsg); 119 MI::ModuleShutdown<CMICmnResources>(IDE_MI_SHTDWN_ERR_RESOURCES, bOk, errMsg); 120 MI::ModuleShutdown<CMICmnLog>(IDS_MI_SHTDWN_ERR_LOG, bOk, errMsg);
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/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonBitSimplify.cpp | 158 static void getInstrDefs(const MachineInstr &MI, RegisterSet &Defs); 159 static void getInstrUses(const MachineInstr &MI, RegisterSet &Uses); 246 void HexagonBitSimplify::getInstrDefs(const MachineInstr &MI, argument 248 for (auto &Op : MI.operands()) { 258 void HexagonBitSimplify::getInstrUses(const MachineInstr &MI, argument 260 for (auto &Op : MI.operands()) { 956 for (auto MI : Instrs) { 957 unsigned Opc = MI->getOpcode(); 964 if (MI->isInlineAsm()) 967 if (!MI [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/Sparc/ |
H A D | SparcInstrInfo.cpp | 44 unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, argument 46 if (MI->getOpcode() == SP::LDri || 47 MI->getOpcode() == SP::LDXri || 48 MI->getOpcode() == SP::LDFri || 49 MI->getOpcode() == SP::LDDFri || 50 MI->getOpcode() == SP::LDQFri) { 51 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() && 52 MI->getOperand(2).getImm() == 0) { 53 FrameIndex = MI 65 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const argument [all...] |
H A D | SparcInstrInfo.h | 57 unsigned isLoadFromStackSlot(const MachineInstr *MI, 65 unsigned isStoreToStackSlot(const MachineInstr *MI,
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/freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/ |
H A D | AArch64CollectLOH.cpp | 249 /// Given a couple (reg, MI) get the corresponding set of instructions from the 252 /// MI and reg, i.e., MI defines reg. 257 const MachineInstr &MI) { 258 return sets[reg][&MI]; 262 /// \return NULL if the couple (reg, MI) is not in sets. 264 const MachineInstr &MI) { 265 InstrToInstrs::const_iterator Res = sets[reg].find(&MI); 298 for (const MachineInstr &MI : MBB) { 299 bool IsADRP = MI 256 getUses(InstrToInstrs *sets, unsigned reg, const MachineInstr &MI) argument 263 getUses(const InstrToInstrs *sets, unsigned reg, const MachineInstr &MI) argument [all...] |
H A D | AArch64FrameLowering.h | 48 MachineBasicBlock::iterator MI, 53 MachineBasicBlock::iterator MI,
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/freebsd-11.0-release/contrib/llvm/tools/clang/include/clang/Lex/ |
H A D | MacroArgs.h | 64 static MacroArgs *create(const MacroInfo *MI, 89 getPreExpArgument(unsigned Arg, const MacroInfo *MI, Preprocessor &PP);
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/freebsd-11.0-release/contrib/llvm/lib/CodeGen/AsmPrinter/ |
H A D | EHStreamer.h | 128 void beginInstruction(const MachineInstr *MI) override {} 133 static bool callToNoUnwindFunction(const MachineInstr *MI);
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/freebsd-11.0-release/contrib/llvm/include/llvm/CodeGen/ |
H A D | LiveIntervalAnalysis.h | 79 /// MI = Indexes->getInstructionFromIndex(RegMaskSlot[N]); 80 /// unsigned OpNum = findRegMaskOperand(MI); 81 /// RegMaskBits[N] = MI->getOperand(OpNum).getRegMask(); 243 SlotIndex InsertMachineInstrInMaps(MachineInstr *MI) { argument 244 return Indexes->insertMachineInstrInMaps(MI); 253 void RemoveMachineInstrFromMaps(MachineInstr *MI) { argument 254 Indexes->removeMachineInstrFromMaps(MI); 257 void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr *NewMI) { argument 258 Indexes->replaceMachineInstrInMaps(MI, NewMI); 291 void handleMove(MachineInstr* MI, boo [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/ |
H A D | Thumb2InstrInfo.h | 66 void expandLoadStackGuard(MachineBasicBlock::iterator MI, 73 ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
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