/freebsd-11.0-release/contrib/llvm/lib/Target/Mips/ |
H A D | MipsAnalyzeImmediate.cpp | 15 MipsAnalyzeImmediate::Inst::Inst(unsigned O, unsigned I) : Opc(O), ImmOpnd(I) {} function in class:MipsAnalyzeImmediate::Inst 18 void MipsAnalyzeImmediate::AddInstr(InstSeqLs &SeqLs, const Inst &I) { 32 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL)); 38 AddInstr(SeqLs, Inst(ORi, Imm & 0xffffULL)); 45 AddInstr(SeqLs, Inst(SLL, Shamt)); 58 AddInstr(SeqLs, Inst(ADDiu, MaskedImm));
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/freebsd-11.0-release/contrib/llvm/lib/Target/X86/InstPrinter/ |
H A D | X86InstComments.cpp | 130 #define CASE_MASK_INS_COMMON(Inst, Suffix, src) \ 131 case X86::V##Inst##Suffix##src: \ 132 case X86::V##Inst##Suffix##src##k: \ 133 case X86::V##Inst##Suffix##src##kz: 135 #define CASE_SSE_INS_COMMON(Inst, src) \ 136 case X86::Inst##src: 138 #define CASE_AVX_INS_COMMON(Inst, Suffix, src) \ 139 case X86::V##Inst##Suffix##src: 141 #define CASE_MOVDUP(Inst, src) \ 142 CASE_MASK_INS_COMMON(Inst, [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Transforms/ObjCARC/ |
H A D | ObjCARCOpts.cpp | 497 bool VisitInstructionBottomUp(Instruction *Inst, BasicBlock *BB, 503 bool VisitInstructionTopDown(Instruction *Inst, 686 Instruction *Inst = &*I++; local 688 ARCInstKind Class = GetBasicARCInstKind(Inst); 690 DEBUG(dbgs() << "Visiting: Class: " << Class << "; " << *Inst << "\n"); local 706 DEBUG(dbgs() << "Erasing no-op cast: " << *Inst << "\n"); 707 EraseInstruction(Inst); 716 CallInst *CI = cast<CallInst>(Inst); 734 CallInst *CI = cast<CallInst>(Inst); 754 if (OptimizeRetainRVCall(F, Inst)) 1100 VisitInstructionBottomUp( Instruction *Inst, BasicBlock *BB, BlotMapVector<Value *, RRInfo> &Retains, BBState &MyStates) argument 1224 Instruction *Inst = &*std::prev(I); local 1251 VisitInstructionTopDown(Instruction *Inst, DenseMap<Value *, RRInfo> &Releases, BBState &MyStates) argument 1815 Instruction *Inst = &*I++; local 1922 Instruction *Inst = &*I++; local 2142 Instruction *Inst = &*I++; local [all...] |
H A D | PtrState.h | 182 void HandlePotentialUse(BasicBlock *BB, Instruction *Inst, const Value *Ptr, 184 bool HandlePotentialAlterRefCount(Instruction *Inst, const Value *Ptr, 200 void HandlePotentialUse(Instruction *Inst, const Value *Ptr, 203 bool HandlePotentialAlterRefCount(Instruction *Inst, const Value *Ptr,
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/freebsd-11.0-release/contrib/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsTargetStreamer.cpp | 803 for (const MCInst &Inst : StoreInsts) 804 getStreamer().EmitInstruction(Inst, STI); 816 MCInst Inst; local 821 Inst.setOpcode(Mips::OR64); 822 Inst.addOperand(MCOperand::createReg(RegOrOffset)); 823 Inst.addOperand(MCOperand::createReg(Mips::GP)); 824 Inst.addOperand(MCOperand::createReg(Mips::ZERO)); 827 Inst.setOpcode(Mips::SD); 828 Inst.addOperand(MCOperand::createReg(Mips::GP)); 829 Inst [all...] |
H A D | MipsAsmBackend.h | 57 /// \param Inst - The instruction to test. 58 bool mayNeedRelaxation(const MCInst &Inst) const override { 75 /// \param Inst - The instruction to relax, which may be the same 78 void relaxInstruction(const MCInst &Inst, MCInst &Res) const override {}
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/freebsd-11.0-release/contrib/llvm/lib/Transforms/Scalar/ |
H A D | LowerAtomic.cpp | 123 Instruction *Inst = &*DI++; variable 124 if (FenceInst *FI = dyn_cast<FenceInst>(Inst)) 126 else if (AtomicCmpXchgInst *CXI = dyn_cast<AtomicCmpXchgInst>(Inst)) 128 else if (AtomicRMWInst *RMWI = dyn_cast<AtomicRMWInst>(Inst)) 130 else if (LoadInst *LI = dyn_cast<LoadInst>(Inst)) { 133 } else if (StoreInst *SI = dyn_cast<StoreInst>(Inst)) {
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H A D | MergedLoadStoreMotion.cpp | 134 void removeInstruction(Instruction *Inst); 183 void MergedLoadStoreMotion::removeInstruction(Instruction *Inst) { argument 186 MD->removeInstruction(Inst); 187 if (LoadInst *LI = dyn_cast<LoadInst>(Inst)) 189 if (Inst->getType()->getScalarType()->isPointerTy()) { 190 MD->invalidateCachedPointerInfo(Inst); 193 Inst->eraseFromParent(); 262 Instruction *Inst = &*BBI; local 265 if (!isa<LoadInst>(Inst) || Inst 416 Instruction *Inst = &*RBI; local [all...] |
H A D | DCE.cpp | 12 // Dead Inst Elimination performs a single pass over the function removing 50 Instruction *Inst = &*DI++; variable 51 if (isInstructionTriviallyDead(Inst, TLI)) { 52 Inst->eraseFromParent();
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H A D | Reg2Mem.cpp | 49 bool valueEscapes(const Instruction *Inst) const { 50 const BasicBlock *BB = Inst->getParent(); 51 for (const User *U : Inst->users()) {
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/freebsd-11.0-release/contrib/llvm/lib/MC/MCDisassembler/ |
H A D | Disassembler.cpp | 151 /// \brief Gets latency information for \p Inst from the itinerary 155 static int getItineraryLatency(LLVMDisasmContext *DC, const MCInst &Inst) { argument 166 const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode()); 170 for (unsigned OpIdx = 0, OpIdxEnd = Inst.getNumOperands(); OpIdx != OpIdxEnd; 177 /// \brief Gets latency information for \p Inst, based on \p DC information. 180 static int getLatency(LLVMDisasmContext *DC, const MCInst &Inst) { argument 190 return getItineraryLatency(DC, Inst); 193 const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode()); 215 /// \brief Emits latency information in DC->CommentStream for \p Inst, based 217 static void emitLatency(LLVMDisasmContext *DC, const MCInst &Inst) { argument 247 MCInst Inst; local [all...] |
/freebsd-11.0-release/contrib/llvm/include/llvm/MC/ |
H A D | MCCodeEmitter.h | 37 /// EncodeInstruction - Encode the given \p Inst to bytes on the output 39 virtual void encodeInstruction(const MCInst &Inst, raw_ostream &OS,
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/freebsd-11.0-release/contrib/llvm/include/llvm/Analysis/ |
H A D | MemoryDependenceAnalysis.h | 105 static MemDepResult getDef(Instruction *Inst) { argument 106 assert(Inst && "Def requires inst"); 107 return MemDepResult(PairTy(Inst, Def)); 109 static MemDepResult getClobber(Instruction *Inst) { argument 110 assert(Inst && "Clobber requires inst"); 111 return MemDepResult(PairTy(Inst, Clobber)); 184 static MemDepResult getDirty(Instruction *Inst) { argument 185 return MemDepResult(PairTy(Inst, Invalid)); 462 void verifyRemoved(Instruction *Inst) const;
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/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonAsmBackend.cpp | 198 /// \param Inst - The instruction to test. 199 bool mayNeedRelaxation(MCInst const &Inst) const override { 200 assert(HexagonMCInstrInfo::isBundle(Inst)); 202 for (auto const &I : HexagonMCInstrInfo::bundleInstructions(Inst)) { 203 auto const &Inst = *I.getInst(); variable 205 if (isInstRelaxable(Inst)) 208 PreviousIsExtender = HexagonMCInstrInfo::isImmext(Inst); 297 void relaxInstruction(MCInst const & Inst, 299 assert(HexagonMCInstrInfo::isBundle(Inst) && 305 for (auto &I : HexagonMCInstrInfo::bundleInstructions(Inst)) { [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCTargetDesc.cpp | 254 bool isUnconditionalBranch(const MCInst &Inst) const override { 256 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL) 258 return MCInstrAnalysis::isUnconditionalBranch(Inst); 261 bool isConditionalBranch(const MCInst &Inst) const override { 263 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL) 265 return MCInstrAnalysis::isConditionalBranch(Inst); 268 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, 271 if (Info->get(Inst [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 84 bool validateInstruction(MCInst &Inst, SmallVectorImpl<SMLoc> &Loc); 1163 void addExpr(MCInst &Inst, const MCExpr *Expr) const { argument 1166 Inst.addOperand(MCOperand::createImm(0)); 1168 Inst.addOperand(MCOperand::createImm(CE->getValue())); 1170 Inst.addOperand(MCOperand::createExpr(Expr)); 1173 void addRegOperands(MCInst &Inst, unsigned N) const { argument 1175 Inst.addOperand(MCOperand::createReg(getReg())); 1178 void addGPR32as64Operands(MCInst &Inst, unsigned N) const { argument 1187 Inst.addOperand(MCOperand::createReg(Reg)); 1190 void addVectorReg64Operands(MCInst &Inst, unsigne argument 1197 addVectorReg128Operands(MCInst &Inst, unsigned N) const argument 1204 addVectorRegLoOperands(MCInst &Inst, unsigned N) const argument 1210 addVectorList64Operands(MCInst &Inst, unsigned N) const argument 1223 addVectorList128Operands(MCInst &Inst, unsigned N) const argument 1235 addVectorIndex1Operands(MCInst &Inst, unsigned N) const argument 1240 addVectorIndexBOperands(MCInst &Inst, unsigned N) const argument 1245 addVectorIndexHOperands(MCInst &Inst, unsigned N) const argument 1250 addVectorIndexSOperands(MCInst &Inst, unsigned N) const argument 1255 addVectorIndexDOperands(MCInst &Inst, unsigned N) const argument 1260 addImmOperands(MCInst &Inst, unsigned N) const argument 1268 addAddSubImmOperands(MCInst &Inst, unsigned N) const argument 1279 addAddSubImmNegOperands(MCInst &Inst, unsigned N) const argument 1291 addCondCodeOperands(MCInst &Inst, unsigned N) const argument 1296 addAdrpLabelOperands(MCInst &Inst, unsigned N) const argument 1305 addAdrLabelOperands(MCInst &Inst, unsigned N) const argument 1310 addUImm12OffsetOperands(MCInst &Inst, unsigned N) const argument 1321 addSImm9Operands(MCInst &Inst, unsigned N) const argument 1327 addSImm7s4Operands(MCInst &Inst, unsigned N) const argument 1333 addSImm7s8Operands(MCInst &Inst, unsigned N) const argument 1339 addSImm7s16Operands(MCInst &Inst, unsigned N) const argument 1345 addImm0_1Operands(MCInst &Inst, unsigned N) const argument 1351 addImm0_7Operands(MCInst &Inst, unsigned N) const argument 1357 addImm1_8Operands(MCInst &Inst, unsigned N) const argument 1363 addImm0_15Operands(MCInst &Inst, unsigned N) const argument 1369 addImm1_16Operands(MCInst &Inst, unsigned N) const argument 1376 addImm0_31Operands(MCInst &Inst, unsigned N) const argument 1382 addImm1_31Operands(MCInst &Inst, unsigned N) const argument 1388 addImm1_32Operands(MCInst &Inst, unsigned N) const argument 1394 addImm0_63Operands(MCInst &Inst, unsigned N) const argument 1400 addImm1_63Operands(MCInst &Inst, unsigned N) const argument 1406 addImm1_64Operands(MCInst &Inst, unsigned N) const argument 1412 addImm0_127Operands(MCInst &Inst, unsigned N) const argument 1418 addImm0_255Operands(MCInst &Inst, unsigned N) const argument 1424 addImm0_65535Operands(MCInst &Inst, unsigned N) const argument 1430 addImm32_63Operands(MCInst &Inst, unsigned N) const argument 1436 addLogicalImm32Operands(MCInst &Inst, unsigned N) const argument 1444 addLogicalImm64Operands(MCInst &Inst, unsigned N) const argument 1451 addLogicalImm32NotOperands(MCInst &Inst, unsigned N) const argument 1459 addLogicalImm64NotOperands(MCInst &Inst, unsigned N) const argument 1467 addSIMDImmType10Operands(MCInst &Inst, unsigned N) const argument 1474 addBranchTarget26Operands(MCInst &Inst, unsigned N) const argument 1488 addPCRelLabel19Operands(MCInst &Inst, unsigned N) const argument 1502 addBranchTarget14Operands(MCInst &Inst, unsigned N) const argument 1516 addFPImmOperands(MCInst &Inst, unsigned N) const argument 1521 addBarrierOperands(MCInst &Inst, unsigned N) const argument 1526 addMRSSystemRegisterOperands(MCInst &Inst, unsigned N) const argument 1532 addMSRSystemRegisterOperands(MCInst &Inst, unsigned N) const argument 1538 addSystemPStateFieldWithImm0_1Operands(MCInst &Inst, unsigned N) const argument 1544 addSystemPStateFieldWithImm0_15Operands(MCInst &Inst, unsigned N) const argument 1550 addSysCROperands(MCInst &Inst, unsigned N) const argument 1555 addPrefetchOperands(MCInst &Inst, unsigned N) const argument 1560 addPSBHintOperands(MCInst &Inst, unsigned N) const argument 1565 addShifterOperands(MCInst &Inst, unsigned N) const argument 1572 addExtendOperands(MCInst &Inst, unsigned N) const argument 1580 addExtend64Operands(MCInst &Inst, unsigned N) const argument 1588 addMemExtendOperands(MCInst &Inst, unsigned N) const argument 1600 addMemExtend8Operands(MCInst &Inst, unsigned N) const argument 1609 addMOVZMovAliasOperands(MCInst &Inst, unsigned N) const argument 1618 addMOVNMovAliasOperands(MCInst &Inst, unsigned N) const argument 3472 validateInstruction(MCInst &Inst, SmallVectorImpl<SMLoc> &Loc) argument 4048 MCInst Inst; local 4297 MCInst Inst; local [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmInstrumentation.cpp | 184 void InstrumentAndEmitInstruction(const MCInst &Inst, 189 InstrumentMOVS(Inst, Operands, Ctx, MII, Out); 193 InstrumentMOV(Inst, Operands, Ctx, MII, Out); 195 RepPrefix = (Inst.getOpcode() == X86::REP_PREFIX); 197 EmitInstruction(Out, Inst); 228 void InstrumentMOVS(const MCInst &Inst, OperandVector &Operands, 230 void InstrumentMOV(const MCInst &Inst, OperandVector &Operands, 238 MCInst Inst; local 239 Inst.setOpcode(Size == 32 ? X86::LEA32r : X86::LEA64r); 240 Inst 347 InstrumentMOVS(const MCInst &Inst, OperandVector &Operands, MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out) argument 374 InstrumentMOV(const MCInst &Inst, OperandVector &Operands, MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out) argument 636 MCInst Inst; local 706 MCInst Inst; local 908 MCInst Inst; local 978 MCInst Inst; local 1032 InstrumentAndEmitInstruction( const MCInst &Inst, OperandVector &Operands, MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out) argument 1038 EmitInstruction(MCStreamer &Out, const MCInst &Inst) argument [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Analysis/ |
H A D | InstCount.cpp | 32 STATISTIC(Num ## OPCODE ## Inst, "Number of " #OPCODE " insts"); 45 void visit##OPCODE(CLASS &) { ++Num##OPCODE##Inst; ++TotalInsts; }
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/freebsd-11.0-release/contrib/llvm/lib/Target/SystemZ/AsmParser/ |
H A D | SystemZAsmParser.cpp | 120 void addExpr(MCInst &Inst, const MCExpr *Expr) const { argument 123 Inst.addOperand(MCOperand::createImm(0)); 125 Inst.addOperand(MCOperand::createImm(CE->getValue())); 127 Inst.addOperand(MCOperand::createExpr(Expr)); 253 void addBDVAddrOperands(MCInst &Inst, unsigned N) const { argument 256 Inst.addOperand(MCOperand::createReg(Mem.Base)); 257 addExpr(Inst, Mem.Disp); 258 Inst.addOperand(MCOperand::createReg(Mem.Index)); 268 void addRegOperands(MCInst &Inst, unsigned N) const { argument 270 Inst 272 addAccessRegOperands(MCInst &Inst, unsigned N) const argument 277 addImmOperands(MCInst &Inst, unsigned N) const argument 281 addBDAddrOperands(MCInst &Inst, unsigned N) const argument 287 addBDXAddrOperands(MCInst &Inst, unsigned N) const argument 294 addBDLAddrOperands(MCInst &Inst, unsigned N) const argument 301 addImmTLSOperands(MCInst &Inst, unsigned N) const argument 787 MCInst Inst; local [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/WebAssembly/MCTargetDesc/ |
H A D | WebAssemblyAsmBackend.cpp | 56 bool mayNeedRelaxation(const MCInst &Inst) const override { return false; } 58 void relaxInstruction(const MCInst &Inst, MCInst &Res) const override {}
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/freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
H A D | R600MCCodeEmitter.cpp | 133 uint64_t Inst = getBinaryCodeForInstr(MI, Fixups, STI); local 137 uint64_t ISAOpCode = Inst & (0x3FFULL << 39); 138 Inst &= ~(0x3FFULL << 39); 139 Inst |= ISAOpCode << 1; 141 Emit(Inst, OS);
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/freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/AsmParser/ |
H A D | AMDGPUAsmParser.cpp | 99 void addImmOperands(MCInst &Inst, unsigned N) const { argument 100 Inst.addOperand(MCOperand::createImm(getImm())); 107 void addRegOperands(MCInst &Inst, unsigned N) const { argument 108 Inst.addOperand(MCOperand::createReg(AMDGPU::getMCReg(getReg(), *Reg.STI))); 111 void addRegOrImmOperands(MCInst &Inst, unsigned N) const { argument 113 addRegOperands(Inst, N); 115 addImmOperands(Inst, N); 118 void addRegWithInputModsOperands(MCInst &Inst, unsigned N) const { argument 119 Inst.addOperand(MCOperand::createImm( 121 addRegOperands(Inst, 124 addSoppBrTargetOperands(MCInst &Inst, unsigned N) const argument 595 checkTargetMatchPredicate(MCInst &Inst) argument 617 MCInst Inst; local 1421 cvtDSOffset01(MCInst &Inst, const OperandVector &Operands) argument 1449 cvtDS(MCInst &Inst, const OperandVector &Operands) argument 1614 cvtFlat(MCInst &Inst, const OperandVector &Operands) argument 1690 cvtMubuf(MCInst &Inst, const OperandVector &Operands) argument 1851 cvtVOP3(MCInst &Inst, const OperandVector &Operands) argument [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUOpenCLImageTypeLoweringPass.cpp | 155 auto Inst = dyn_cast<CallInst>(Use.getUser()); local 156 if (!Inst) { 160 Function *F = Inst->getCalledFunction(); 176 Inst->replaceAllUsesWith(Replacement); 177 InstsToErase.push_back(Inst); 188 auto Inst = dyn_cast<CallInst>(Use.getUser()); local 189 if (!Inst) { 193 Function *F = Inst->getCalledFunction(); 205 Inst->replaceAllUsesWith(Replacement); 206 InstsToErase.push_back(Inst); [all...] |
H A D | AMDGPUPromoteAlloca.cpp | 137 static bool canVectorizeInst(Instruction *Inst, User *User) { argument 138 switch (Inst->getOpcode()) { 145 StoreInst *SI = cast<StoreInst>(Inst); 205 Instruction *Inst = cast<Instruction>(*I); local 206 IRBuilder<> Builder(Inst); 207 switch (Inst->getOpcode()) { 209 Value *Ptr = Inst->getOperand(0); 214 Inst->replaceAllUsesWith(ExtractElement); 215 Inst->eraseFromParent(); 219 Value *Ptr = Inst [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/X86/ |
H A D | X86MCInstLower.cpp | 89 void X86AsmPrinter::StackMapShadowTracker::count(MCInst &Inst, argument 95 CodeEmitter->encodeInstruction(Inst, VecOS, Fixups, STI); 111 void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) { argument 112 OutStreamer->EmitInstruction(Inst, getSubtargetInfo()); 113 SMShadowTracker.count(Inst, getSubtargetInfo()); 300 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) { argument 301 unsigned ImmOp = Inst.getNumOperands() - 1; 302 assert(Inst.getOperand(0).isReg() && 303 (Inst.getOperand(ImmOp).isImm() || Inst 322 SimplifyMOVSX(MCInst &Inst) argument 349 SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst, unsigned Opcode) argument [all...] |