AArch64/AsmParser/AArch64AsmParser.cpp

84   bool validateInstruction(MCInst &Inst, SmallVectorImpl<SMLoc> &Loc);
1163   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1166       Inst.addOperand(MCOperand::createImm(0));
1168       Inst.addOperand(MCOperand::createImm(CE->getValue()));
1170       Inst.addOperand(MCOperand::createExpr(Expr));
1173   void addRegOperands(MCInst &Inst, unsigned N) const {
1175     Inst.addOperand(MCOperand::createReg(getReg()));
1178   void addGPR32as64Operands(MCInst &Inst, unsigned N) const {
1187     Inst.addOperand(MCOperand::createReg(Reg));
1190   void addVectorReg64Operands(MCInst &Inst, unsigned N) const {
1194     Inst.addOperand(MCOperand::createReg(AArch64::D0 + getReg() - AArch64::Q0));
1197   void addVectorReg128Operands(MCInst &Inst, unsigned N) const {
1201     Inst.addOperand(MCOperand::createReg(getReg()));
1204   void addVectorRegLoOperands(MCInst &Inst, unsigned N) const {
1206     Inst.addOperand(MCOperand::createReg(getReg()));
1210   void addVectorList64Operands(MCInst &Inst, unsigned N) const {
1218     Inst.addOperand(
1223   void addVectorList128Operands(MCInst &Inst, unsigned N) const {
1231     Inst.addOperand(
1235   void addVectorIndex1Operands(MCInst &Inst, unsigned N) const {
1237     Inst.addOperand(MCOperand::createImm(getVectorIndex()));
1240   void addVectorIndexBOperands(MCInst &Inst, unsigned N) const {
1242     Inst.addOperand(MCOperand::createImm(getVectorIndex()));
1245   void addVectorIndexHOperands(MCInst &Inst, unsigned N) const {
1247     Inst.addOperand(MCOperand::createImm(getVectorIndex()));
1250   void addVectorIndexSOperands(MCInst &Inst, unsigned N) const {
1252     Inst.addOperand(MCOperand::createImm(getVectorIndex()));
1255   void addVectorIndexDOperands(MCInst &Inst, unsigned N) const {
1257     Inst.addOperand(MCOperand::createImm(getVectorIndex()));
1260   void addImmOperands(MCInst &Inst, unsigned N) const {
1265     addExpr(Inst, getImm());
1268   void addAddSubImmOperands(MCInst &Inst, unsigned N) const {
1271       addExpr(Inst, getShiftedImmVal());
1272       Inst.addOperand(MCOperand::createImm(getShiftedImmShift()));
1274       addExpr(Inst, getImm());
1275       Inst.addOperand(MCOperand::createImm(0));
1279   void addAddSubImmNegOperands(MCInst &Inst, unsigned N) const {
1287     Inst.addOperand(MCOperand::createImm(Val));
1288     Inst.addOperand(MCOperand::createImm(ShiftAmt));
1291   void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1293     Inst.addOperand(MCOperand::createImm(getCondCode()));
1296   void addAdrpLabelOperands(MCInst &Inst, unsigned N) const {
1300       addExpr(Inst, getImm());
1302       Inst.addOperand(MCOperand::createImm(MCE->getValue() >> 12));
1305   void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1306     addImmOperands(Inst, N);
1310   void addUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1315       Inst.addOperand(MCOperand::createExpr(getImm()));
1318     Inst.addOperand(MCOperand::createImm(MCE->getValue() / Scale));
1321   void addSImm9Operands(MCInst &Inst, unsigned N) const {
1324     Inst.addOperand(MCOperand::createImm(MCE->getValue()));
1327   void addSImm7s4Operands(MCInst &Inst, unsigned N) const {
1330     Inst.addOperand(MCOperand::createImm(MCE->getValue() / 4));
1333   void addSImm7s8Operands(MCInst &Inst, unsigned N) const {
1336     Inst.addOperand(MCOperand::createImm(MCE->getValue() / 8));
1339   void addSImm7s16Operands(MCInst &Inst, unsigned N) const {
1342     Inst.addOperand(MCOperand::createImm(MCE->getValue() / 16));
1345   void addImm0_1Operands(MCInst &Inst, unsigned N) const {
1348     Inst.addOperand(MCOperand::createImm(MCE->getValue()));
1351   void addImm0_7Operands(MCInst &Inst, unsigned N) const {
1354     Inst.addOperand(MCOperand::createImm(MCE->getValue()));
1357   void addImm1_8Operands(MCInst &Inst, unsigned N) const {
1360     Inst.addOperand(MCOperand::createImm(MCE->getValue()));
1363   void addImm0_15Operands(MCInst &Inst, unsigned N) const {
1366     Inst.addOperand(MCOperand::createImm(MCE->getValue()));
1369   void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1373     Inst.addOperand(MCOperand::createImm(MCE->getValue()));
1376   void addImm0_31Operands(MCInst &Inst, unsigned N) const {
1379     Inst.addOperand(MCOperand::createImm(MCE->getValue()));
1382   void addImm1_31Operands(MCInst &Inst, unsigned N) const {
1385     Inst.addOperand(MCOperand::createImm(MCE->getValue()));
1388   void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1391     Inst.addOperand(MCOperand::createImm(MCE->getValue()));
1394   void addImm0_63Operands(MCInst &Inst, unsigned N) const {
1397     Inst.addOperand(MCOperand::createImm(MCE->getValue()));
1400   void addImm1_63Operands(MCInst &Inst, unsigned N) const {
1403     Inst.addOperand(MCOperand::createImm(MCE->getValue()));
1406   void addImm1_64Operands(MCInst &Inst, unsigned N) const {
1409     Inst.addOperand(MCOperand::createImm(MCE->getValue()));
1412   void addImm0_127Operands(MCInst &Inst, unsigned N) const {
1415     Inst.addOperand(MCOperand::createImm(MCE->getValue()));
1418   void addImm0_255Operands(MCInst &Inst, unsigned N) const {
1421     Inst.addOperand(MCOperand::createImm(MCE->getValue()));
1424   void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
1427     Inst.addOperand(MCOperand::createImm(MCE->getValue()));
1430   void addImm32_63Operands(MCInst &Inst, unsigned N) const {
1433     Inst.addOperand(MCOperand::createImm(MCE->getValue()));
1436   void addLogicalImm32Operands(MCInst &Inst, unsigned N) const {
1441     Inst.addOperand(MCOperand::createImm(encoding));
1444   void addLogicalImm64Operands(MCInst &Inst, unsigned N) const {
1448     Inst.addOperand(MCOperand::createImm(encoding));
1451   void addLogicalImm32NotOperands(MCInst &Inst, unsigned N) const {
1456     Inst.addOperand(MCOperand::createImm(encoding));
1459   void addLogicalImm64NotOperands(MCInst &Inst, unsigned N) const {
1464     Inst.addOperand(MCOperand::createImm(encoding));
1467   void addSIMDImmType10Operands(MCInst &Inst, unsigned N) const {
1471     Inst.addOperand(MCOperand::createImm(encoding));
1474   void addBranchTarget26Operands(MCInst &Inst, unsigned N) const {
1481       addExpr(Inst, getImm());
1485     Inst.addOperand(MCOperand::createImm(MCE->getValue() >> 2));
1488   void addPCRelLabel19Operands(MCInst &Inst, unsigned N) const {
1495       addExpr(Inst, getImm());
1499     Inst.addOperand(MCOperand::createImm(MCE->getValue() >> 2));
1502   void addBranchTarget14Operands(MCInst &Inst, unsigned N) const {
1509       addExpr(Inst, getImm());
1513     Inst.addOperand(MCOperand::createImm(MCE->getValue() >> 2));
1516   void addFPImmOperands(MCInst &Inst, unsigned N) const {
1518     Inst.addOperand(MCOperand::createImm(getFPImm()));
1521   void addBarrierOperands(MCInst &Inst, unsigned N) const {
1523     Inst.addOperand(MCOperand::createImm(getBarrier()));
1526   void addMRSSystemRegisterOperands(MCInst &Inst, unsigned N) const {
1529     Inst.addOperand(MCOperand::createImm(SysReg.MRSReg));
1532   void addMSRSystemRegisterOperands(MCInst &Inst, unsigned N) const {
1535     Inst.addOperand(MCOperand::createImm(SysReg.MSRReg));
1538   void addSystemPStateFieldWithImm0_1Operands(MCInst &Inst, unsigned N) const {
1541     Inst.addOperand(MCOperand::createImm(SysReg.PStateField));
1544   void addSystemPStateFieldWithImm0_15Operands(MCInst &Inst, unsigned N) const {
1547     Inst.addOperand(MCOperand::createImm(SysReg.PStateField));
1550   void addSysCROperands(MCInst &Inst, unsigned N) const {
1552     Inst.addOperand(MCOperand::createImm(getSysCR()));
1555   void addPrefetchOperands(MCInst &Inst, unsigned N) const {
1557     Inst.addOperand(MCOperand::createImm(getPrefetch()));
1560   void addPSBHintOperands(MCInst &Inst, unsigned N) const {
1562     Inst.addOperand(MCOperand::createImm(getPSBHint()));
1565   void addShifterOperands(MCInst &Inst, unsigned N) const {
1569     Inst.addOperand(MCOperand::createImm(Imm));
1572   void addExtendOperands(MCInst &Inst, unsigned N) const {
1577     Inst.addOperand(MCOperand::createImm(Imm));
1580   void addExtend64Operands(MCInst &Inst, unsigned N) const {
1585     Inst.addOperand(MCOperand::createImm(Imm));
1588   void addMemExtendOperands(MCInst &Inst, unsigned N) const {
1592     Inst.addOperand(MCOperand::createImm(IsSigned));
1593     Inst.addOperand(MCOperand::createImm(getShiftExtendAmount() != 0));
1600   void addMemExtend8Operands(MCInst &Inst, unsigned N) const {
1604     Inst.addOperand(MCOperand::createImm(IsSigned));
1605     Inst.addOperand(MCOperand::createImm(hasShiftExtendAmount()));
1609   void addMOVZMovAliasOperands(MCInst &Inst, unsigned N) const {
1614     Inst.addOperand(MCOperand::createImm((Value >> Shift) & 0xffff));
1618   void addMOVNMovAliasOperands(MCInst &Inst, unsigned N) const {
1623     Inst.addOperand(MCOperand::createImm((~Value >> Shift) & 0xffff));
3472 bool AArch64AsmParser::validateInstruction(MCInst &Inst,
3478   switch (Inst.getOpcode()) {
3484     unsigned Rt = Inst.getOperand(1).getReg();
3485     unsigned Rt2 = Inst.getOperand(2).getReg();
3486     unsigned Rn = Inst.getOperand(3).getReg();
3501     unsigned Rt = Inst.getOperand(0).getReg();
3502     unsigned Rt2 = Inst.getOperand(1).getReg();
3514     unsigned Rt = Inst.getOperand(1).getReg();
3515     unsigned Rt2 = Inst.getOperand(2).getReg();
3530     unsigned Rt = Inst.getOperand(1).getReg();
3531     unsigned Rt2 = Inst.getOperand(2).getReg();
3532     unsigned Rn = Inst.getOperand(3).getReg();
3563     unsigned Rt = Inst.getOperand(1).getReg();
3564     unsigned Rn = Inst.getOperand(2).getReg();
3582     unsigned Rt = Inst.getOperand(1).getReg();
3583     unsigned Rn = Inst.getOperand(2).getReg();
3594   switch (Inst.getOpcode()) {
3605     if (Inst.getOperand(2).isExpr()) {
3606       const MCExpr *Expr = Inst.getOperand(2).getExpr();
3617           Inst.getOpcode() == AArch64::ADDXri)
3629           (Inst.getOpcode() == AArch64::ADDXri ||
3630           Inst.getOpcode() == AArch64::ADDWri))
4048   MCInst Inst;
4052       MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm, 1);
4063         MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm, 0);
4084     if (validateInstruction(Inst, OperandLocs))
4087     Inst.setLoc(IDLoc);
4088     Out.EmitInstruction(Inst, getSTI());
4297   MCInst Inst;
4298   Inst.setOpcode(AArch64::TLSDESCCALL);
4299   Inst.addOperand(MCOperand::createExpr(Expr));
4301   getParser().getStreamer().EmitInstruction(Inst, getSTI());