| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FastISel.cpp | 2042 TII.getRegClass(II, OpNum, &TRI, *FuncInfo.MF);
2250 const TargetRegisterClass *RC = MRI.getRegClass(Op0);
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| H A D | SelectionDAGISel.cpp | 531 MRI.constrainRegClass(To, MRI.getRegClass(From));
677 MRI.constrainRegClass(To, MRI.getRegClass(From));
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | LiveDebugVariables.cpp | 1204 const TargetRegisterClass *TRC = MRI.getRegClass(VirtReg);
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| H A D | ScheduleDAGInstrs.cpp | 370 const TargetRegisterClass &RC = *MRI.getRegClass(Reg);
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| H A D | LiveIntervals.cpp | 1671 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg);
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| H A D | TargetLoweringBase.cpp | 1128 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIPeepholeSDWA.cpp | 1186 !TRI->hasVGPRs(TRI->getRegClass(Desc.OpInfo[I].RegClass)))
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| H A D | AMDGPUISelDAGToDAG.cpp | 570 return MRI.getRegClass(Reg);
592 return Subtarget->getRegisterInfo()->getRegClass(RegClass);
597 Subtarget->getRegisterInfo()->getRegClass(RCID);
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| H A D | SILoadStoreOptimizer.cpp | 1607 const auto *CarryRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelDAGToDAG.cpp | 119 if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg))
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| H A D | MipsFastISel.cpp | 1733 if (!MRI.getRegClass(SrcReg)->contains(DestReg))
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| H A D | MipsSEISelLowering.cpp | 3524 MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())
3576 MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 1248 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
1762 if (MRI.getRegClass(OpReg) == &X86::VK1RegClass) {
2108 if (MRI.getRegClass(CondReg) == &X86::VK1RegClass) {
2326 if (MRI.getRegClass(CondReg) == &X86::VK1RegClass) {
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIParser.cpp | 281 const auto *RC = TRI->getRegClass(I);
305 PerTargetMIParsingState::getRegClass(StringRef Name) { function in class:PerTargetMIParsingState
1280 const TargetRegisterClass *RC = PFS.Target.getRegClass(Name);
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| H A D | AMDGPUInstPrinter.cpp | 580 unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID));
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 1638 return isRegKind() && AsmParser->getMRI()->getRegClass(RCID).contains(getReg());
1895 static int getRegClass(RegisterKind Is, unsigned RegWidth) { function
2130 int RCID = getRegClass(RegKind, RegWidth);
2135 const MCRegisterClass RC = TRI->getRegClass(RCID);
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMAsmPrinter.cpp | 374 ARM::GPRPairRegClass.hasSubClassEq(TRI->getRegClass(RC))) {
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| H A D | ARMLoadStoreOptimizer.cpp | 2330 const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF);
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| H A D | ARMFrameLowering.cpp | 1533 const TargetRegisterClass *RegClass = TII.getRegClass(MCID, i, TRI, MF);
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| H A D | ARMBaseInstrInfo.cpp | 2247 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
3299 const TargetRegisterClass *TRC = MRI->getRegClass(Reg);
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/Disassembler/ |
| H A D | MipsDisassembler.cpp | 583 return *(RegInfo->getRegClass(RC).begin() + RegNo);
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstExtenders.cpp | 1927 MRI->getRegClass(Op.getReg()) != &Hexagon::PredRegsRegClass)
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| /freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.cpp | 1262 CodeGenRegisterClass *CodeGenRegBank::getRegClass(Record *Def) { function in class:CodeGenRegBank
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| H A D | GlobalISelEmitter.cpp | 4316 CodeGenRegisterClass *RC = CGRegs.getRegClass(RCDef);
4505 CodeGenRegisterClass *RC = CGRegs.getRegClass(RCRec);
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1436 uint32_t Reg = RI->getRegClass(AArch64::GPR32RegClassID).getRegister(
1448 uint32_t Reg = RI->getRegClass(AArch64::GPR64RegClassID).getRegister(
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