/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCMCInstLower.cpp | 87 return MCOperand::createReg(MO.getReg());
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRMCInstLower.cpp | 76 MCOp = MCOperand::createReg(MO.getReg());
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/AsmParser/ |
H A D | BPFAsmParser.cpp | 188 Inst.addOperand(MCOperand::createReg(getReg())); 204 static std::unique_ptr<BPFOperand> createReg(unsigned RegNo, SMLoc S, function in struct:__anon2197::BPFOperand 420 Operands.push_back(BPFOperand::createReg(RegNo, S, E)); 459 Operands.push_back(BPFOperand::createReg(RegNo, NameLoc, E));
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
H A D | AArch64Disassembler.cpp | 321 Inst.addOperand(MCOperand::createReg(Register)); 350 Inst.addOperand(MCOperand::createReg(Register)); 371 Inst.addOperand(MCOperand::createReg(Register)); 392 Inst.addOperand(MCOperand::createReg(Register)); 413 Inst.addOperand(MCOperand::createReg(Register)); 434 Inst.addOperand(MCOperand::createReg(Register)); 445 Inst.addOperand(MCOperand::createReg(Register)); 457 Inst.addOperand(MCOperand::createReg(Register)); 478 Inst.addOperand(MCOperand::createReg(Register)); 491 Inst.addOperand(MCOperand::createReg(Registe [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/AsmParser/ |
H A D | PPCAsmParser.cpp | 415 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); 420 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()])); 425 Inst.addOperand(MCOperand::createReg(XRegs[getReg()])); 430 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()])); 449 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); 454 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); 459 Inst.addOperand(MCOperand::createReg(VFRegs[getReg()])); 464 Inst.addOperand(MCOperand::createReg(VRegs[getReg()])); 469 Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()])); 474 Inst.addOperand(MCOperand::createReg(VSFReg [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMAsmPrinter.cpp | 1402 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); 1423 TmpInst.addOperand(MCOperand::createReg(0)); 1425 TmpInst.addOperand(MCOperand::createReg(0)); 1434 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); 1435 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg())); 1455 TmpInst.addOperand(MCOperand::createReg(0)); 1457 TmpInst.addOperand(MCOperand::createReg(0)); 1760 TmpInst.addOperand(MCOperand::createReg(ARM::PC)); 1761 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); 1764 TmpInst.addOperand(MCOperand::createReg( [all...] |
H A D | ARMMCInstLower.cpp | 81 MCOp = MCOperand::createReg(MO.getReg());
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsAsmPrinter.cpp | 145 TmpInst0.addOperand(MCOperand::createReg(ZeroReg)); 870 I.addOperand(MCOperand::createReg(Reg)); 889 I.addOperand(MCOperand::createReg(Reg1)); 890 I.addOperand(MCOperand::createReg(Reg2)); 899 I.addOperand(MCOperand::createReg(Reg1)); 900 I.addOperand(MCOperand::createReg(Reg2)); 901 I.addOperand(MCOperand::createReg(Reg3));
|
H A D | MipsMCInstLower.cpp | 186 return MCOperand::createReg(MO.getReg());
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 738 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 743 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 837 MI.insert(CCI, MCOperand::createReg(0)); 839 MI.insert(CCI, MCOperand::createReg(ARM::CPSR)); 854 MI.insert(VCCI, MCOperand::createReg(0)); 856 MI.insert(VCCI, MCOperand::createReg(ARM::P0)); 1133 Inst.addOperand(MCOperand::createReg(Register)); 1147 Inst.addOperand(MCOperand::createReg(Register)); 1171 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 1186 Inst.addOperand(MCOperand::createReg(AR [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64MCInstLower.cpp | 261 MCOp = MCOperand::createReg(MO.getReg()); 309 OutMI.addOperand(MCOperand::createReg(AArch64::LR)); 314 OutMI.addOperand(MCOperand::createReg(AArch64::LR));
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/AsmParser/ |
H A D | SystemZAsmParser.cpp | 169 createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) { function in class:__anon2401::SystemZOperand 297 Inst.addOperand(MCOperand::createReg(getReg())); 306 Inst.addOperand(MCOperand::createReg(Mem.Base)); 312 Inst.addOperand(MCOperand::createReg(Mem.Base)); 314 Inst.addOperand(MCOperand::createReg(Mem.Index)); 319 Inst.addOperand(MCOperand::createReg(Mem.Base)); 326 Inst.addOperand(MCOperand::createReg(Mem.Base)); 328 Inst.addOperand(MCOperand::createReg(Mem.Length.Reg)); 333 Inst.addOperand(MCOperand::createReg(Mem.Base)); 335 Inst.addOperand(MCOperand::createReg(Me [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/ |
H A D | HexagonDisassembler.cpp | 524 Inst.addOperand(MCOperand::createReg(Table[RegNo])); 668 Inst.addOperand(MCOperand::createReg(Register)); 696 Inst.addOperand(MCOperand::createReg(Register)); 714 Inst.addOperand(MCOperand::createReg(Register)); 774 Inst.addOperand(MCOperand::createReg(Register)); 800 Inst.addOperand(MCOperand::createReg(Register));
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonAsmPrinter.cpp | 285 Inst.addOperand(MCOperand::createReg(Hexagon::R0)); 466 TmpInst.addOperand(MCOperand::createReg(High)); 467 TmpInst.addOperand(MCOperand::createReg(Low)); 544 MappedInst.addOperand(MCOperand::createReg(Low)); 556 MappedInst.addOperand(MCOperand::createReg(Low)); 570 MappedInst.addOperand(MCOperand::createReg(Low));
|
H A D | HexagonMCInstLower.cpp | 127 MCO = MCOperand::createReg(MO.getReg());
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcAsmPrinter.cpp | 179 MCOperand MCRegOP = MCOperand::createReg(MO.getReg()); 212 MCOperand RegO7 = MCOperand::createReg(SP::O7); 226 MCOperand RegO7 = MCOperand::createReg(SP::O7);
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/AsmParser/ |
H A D | LanaiAsmParser.cpp | 402 Inst.addOperand(MCOperand::createReg(getReg())); 433 Inst.addOperand(MCOperand::createReg(getMemBaseReg())); 441 Inst.addOperand(MCOperand::createReg(getMemBaseReg())); 443 Inst.addOperand(MCOperand::createReg(getMemOffsetReg())); 592 static std::unique_ptr<LanaiOperand> createReg(unsigned RegNum, SMLoc Start, function in struct:__anon2281::LanaiOperand 703 return LanaiOperand::createReg(RegNum, Start, End);
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/Disassembler/ |
H A D | MSP430Disassembler.cpp | 80 MI.addOperand(MCOperand::createReg(Reg)); 98 MI.addOperand(MCOperand::createReg(Reg));
|
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MC/ |
H A D | MCInst.h | 115 static MCOperand createReg(unsigned Reg) { function in class:llvm::MCOperand
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCMCInstLower.cpp | 173 OutMO = MCOperand::createReg(MO.getReg());
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/ |
H A D | AMDGPUDisassembler.cpp | 410 MCOperand::createReg(MI.getOperand(Tied).getReg()), 574 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 578 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 583 MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0); 610 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI));
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/ |
H A D | SparcAsmParser.cpp | 335 Inst.addOperand(MCOperand::createReg(getReg())); 357 Inst.addOperand(MCOperand::createReg(getMemBase())); 360 Inst.addOperand(MCOperand::createReg(getMemOffsetReg())); 366 Inst.addOperand(MCOperand::createReg(getMemBase())); 537 MCOperand PrevReg = MCOperand::createReg(Sparc::G0);
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 1051 Inst.addOperand(MCOperand::createReg(getGPR32Reg())); 1056 Inst.addOperand(MCOperand::createReg(getGPR32Reg())); 1061 Inst.addOperand(MCOperand::createReg(getGPR32Reg())); 1066 Inst.addOperand(MCOperand::createReg(getGPRMM16Reg())); 1071 Inst.addOperand(MCOperand::createReg(getGPRMM16Reg())); 1076 Inst.addOperand(MCOperand::createReg(getGPRMM16Reg())); 1081 Inst.addOperand(MCOperand::createReg(getGPRMM16Reg())); 1087 Inst.addOperand(MCOperand::createReg(getGPRMM16Reg())); 1095 Inst.addOperand(MCOperand::createReg(getGPR64Reg())); 1100 Inst.addOperand(MCOperand::createReg(getAFGR64Re [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/AsmParser/ |
H A D | MSP430AsmParser.cpp | 129 Inst.addOperand(MCOperand::createReg(Reg)); 153 Inst.addOperand(MCOperand::createReg(Mem.Reg));
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/ |
H A D | HexagonAsmParser.cpp | 380 Inst.addOperand(MCOperand::createReg(getReg())); 1321 Inst.addOperand(MCOperand::createReg(Hexagon::R0)); 1387 Inst.addOperand(MCOperand::createReg(matchRegister(Reg2))); 1402 Inst.addOperand(MCOperand::createReg(matchRegister(Reg2))); 1418 Inst.addOperand(MCOperand::createReg(matchRegister(Reg2))); 1433 Inst.addOperand(MCOperand::createReg(MatchRegisterName(R2))); 1753 TmpInst.addOperand(MCOperand::createReg(matchRegister(Reg2))); 1897 TmpInst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
|