/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 700 const SystemZInstrInfo *TII = local 740 if (TII->isRxSBGMask(Value, SplatBitSize, Start, End)) { 6727 const SystemZInstrInfo *TII) { 6736 BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(SystemZ::LA), Reg) 6796 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); local 6830 BuildMI(*SinkMBB, SinkInsertionPoint, DL, TII->get(SystemZ::PHI), DestReg) 6846 const SystemZInstrInfo *TII = local 6909 BuildMI(MBB, MI.getDebugLoc(), TII->get(SystemZ::BRC)) 6943 const SystemZInstrInfo *TII = local 6954 StoreOpcode = TII 6726 forceReg(MachineInstr &MI, MachineOperand &Base, const SystemZInstrInfo *TII) argument 7034 const SystemZInstrInfo *TII = local 7153 const SystemZInstrInfo *TII = local 7268 const SystemZInstrInfo *TII = local 7392 const SystemZInstrInfo *TII = local 7420 const SystemZInstrInfo *TII = local 7450 const SystemZInstrInfo *TII = local 7630 const SystemZInstrInfo *TII = local 7691 const SystemZInstrInfo *TII = Subtarget.getInstrInfo(); local 7738 const SystemZInstrInfo *TII = local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | AggressiveAntiDepBreaker.h | 120 const TargetInstrInfo *TII; member in class:llvm::AggressiveAntiDepBreaker
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H A D | ExecutionDomainFix.cpp | 117 TII->setExecutionDomain(*dv->Instrs.pop_back_val(), domain); 224 std::pair<uint16_t, uint16_t> DomP = TII->getExecutionDomain(*MI); 322 TII->setExecutionDomain(*mi, domain); 417 TII = MF->getSubtarget().getInstrInfo();
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H A D | SplitKit.h | 101 const TargetInstrInfo &TII; member in class:llvm::SplitAnalysis 264 const TargetInstrInfo &TII; member in class:llvm::SplitEditor
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H A D | DFAPacketizer.cpp | 150 : MF(mf), TII(mf.getSubtarget().getInstrInfo()), AA(aa) { 151 ResourceTracker = TII->CreateTargetScheduleState(MF.getSubtarget());
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H A D | UnreachableBlockElim.cpp | 195 const TargetInstrInfo *TII = F.getSubtarget().getInstrInfo(); local 197 TII->get(TargetOpcode::COPY), OutputReg)
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H A D | PHIElimination.cpp | 263 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); local 268 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg); 285 PHICopy = TII->createPHIDestinationCopy(MBB, AfterPHIsIt, MPhi->getDebugLoc(), 406 TII->get(TargetOpcode::IMPLICIT_DEF), 415 TII->createPHISourceCopy(opBlock, InsertPos, MPhi->getDebugLoc(),
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.h | 31 const TargetInstrInfo *TII; member in class:llvm::InstrEmitter
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ExecutionDomainFix.h | 113 const TargetInstrInfo *TII;
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H A D | TailDuplicator.h | 39 const TargetInstrInfo *TII; member in class:llvm::TailDuplicator
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H A D | DFAPacketizer.h | 115 const TargetInstrInfo *TII; member in class:llvm::VLIWPacketizerList
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | GCNHazardRecognizer.h | 48 const SIInstrInfo &TII; member in class:llvm::final
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H A D | AMDGPUTargetMachine.cpp | 263 DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI)); 264 DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI)); 273 DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI)); 274 DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI)); 287 DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI)); 288 DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI)); 560 DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI)); 561 DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
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H A D | SIISelLowering.cpp | 2001 const TargetInstrInfo *TII = Subtarget->getInstrInfo(); local 2016 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR) 2022 TII->get(TargetOpcode::COPY), *I) 3038 const SIInstrInfo *TII = getSubtarget()->getInstrInfo(); local 3045 MI.setDesc(TII->getKillTerminatorFromPseudo(MI.getOpcode())); 3059 MI.setDesc(TII->getKillTerminatorFromPseudo(MI.getOpcode())); 3109 const SIInstrInfo *TII = getSubtarget()->getInstrInfo(); local 3113 BuildMI(*MBB, E, MI.getDebugLoc(), TII->get(AMDGPU::S_WAITCNT)) 3129 const SIInstrInfo *TII = getSubtarget()->getInstrInfo(); local 3132 if (MachineOperand *Src = TII 3170 emitLoadM0FromVGPRLoop( const SIInstrInfo *TII, MachineRegisterInfo &MRI, MachineBasicBlock &OrigBB, MachineBasicBlock &LoopBB, const DebugLoc &DL, const MachineOperand &IdxReg, unsigned InitReg, unsigned ResultReg, unsigned PhiReg, unsigned InitSaveExecReg, int Offset, bool UseGPRIdxMode, bool IsIndirectSrc) argument 3276 loadM0FromVGPR(const SIInstrInfo *TII, MachineBasicBlock &MBB, MachineInstr &MI, unsigned InitResultReg, unsigned PhiReg, int Offset, bool UseGPRIdxMode, bool IsIndirectSrc) argument 3338 setM0ToIndexFromSGPR(const SIInstrInfo *TII, MachineRegisterInfo &MRI, MachineInstr &MI, int Offset, bool UseGPRIdxMode, bool IsIndirectSrc) argument 3398 const SIInstrInfo *TII = ST.getInstrInfo(); local 3489 const SIInstrInfo *TII = ST.getInstrInfo(); local 3589 const SIInstrInfo *TII = getSubtarget()->getInstrInfo(); local 3794 const SIInstrInfo *TII = getSubtarget()->getInstrInfo(); local 3816 const SIInstrInfo *TII = getSubtarget()->getInstrInfo(); local 8160 const SIInstrInfo *TII = getSubtarget()->getInstrInfo(); local 8392 const SIInstrInfo *TII = getSubtarget()->getInstrInfo(); local 8489 const SIInstrInfo *TII = getSubtarget()->getInstrInfo(); local 9129 const SIInstrInfo *TII = getSubtarget()->getInstrInfo(); local 10345 const SIInstrInfo *TII = getSubtarget()->getInstrInfo(); local 10438 const SIInstrInfo *TII = getSubtarget()->getInstrInfo(); local 10523 const SIInstrInfo *TII = getSubtarget()->getInstrInfo(); local 10760 const SIInstrInfo *TII = ST.getInstrInfo(); local 10811 const SIInstrInfo *TII = getSubtarget()->getInstrInfo(); local [all...] |
H A D | AMDGPUAsmPrinter.cpp | 571 const SIInstrInfo *TII = STM.getInstrInfo(); local 583 CodeSize += TII->getInstSizeInBytes(MI); 591 const SIInstrInfo &TII, 594 if (!UseOp.isImplicit() || !TII.isFLAT(*UseOp.getParent())) 620 const SIInstrInfo *TII = ST.getInstrInfo(); local 621 const SIRegisterInfo &TRI = TII->getRegisterInfo(); 633 (!hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR) && 634 !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_LO) && 635 !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_HI))) { 864 = TII 590 hasAnyNonFlatUseOfReg(const MachineRegisterInfo &MRI, const SIInstrInfo &TII, unsigned Reg) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCBranchCoalescing.cpp | 151 const TargetInstrInfo *TII; member in class:__anon2351::PPCBranchCoalescing 220 TII = MF.getSubtarget().getInstrInfo(); 239 if (TII->analyzeBranch(*Cand.BranchBlock, Cand.BranchTargetBlock, FalseMBB, 241 LLVM_DEBUG(dbgs() << "TII unable to Analyze Branch - skip\n"); 364 if (TII->produceSameValue(*Op1Def, *Op2Def, MRI)) {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyFixIrreducibleControlFlow.cpp | 355 const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo(); local 357 BuildMI(Dispatch, DebugLoc(), TII.get(WebAssembly::BR_TABLE_I32)); 442 BuildMI(Routing, DebugLoc(), TII.get(WebAssembly::CONST_I32), Reg) 444 BuildMI(Routing, DebugLoc(), TII.get(WebAssembly::BR)).addMBB(Dispatch);
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H A D | WebAssemblyISelLowering.cpp | 346 const TargetInstrInfo &TII, 401 BuildMI(BB, DL, TII.get(Abs), Tmp0).addReg(InReg); 403 BuildMI(BB, DL, TII.get(FConst), Tmp1) 405 BuildMI(BB, DL, TII.get(LT), CmpReg).addReg(Tmp0).addReg(Tmp1); 413 BuildMI(BB, DL, TII.get(FConst), Tmp1) 415 BuildMI(BB, DL, TII.get(GE), SecondCmpReg).addReg(Tmp0).addReg(Tmp1); 416 BuildMI(BB, DL, TII.get(And), AndReg).addReg(CmpReg).addReg(SecondCmpReg); 420 BuildMI(BB, DL, TII.get(Eqz), EqzReg).addReg(CmpReg); 424 BuildMI(BB, DL, TII.get(WebAssembly::BR_IF)).addMBB(TrueMBB).addReg(EqzReg); 425 BuildMI(FalseMBB, DL, TII 344 LowerFPToInt(MachineInstr &MI, DebugLoc DL, MachineBasicBlock *BB, const TargetInstrInfo &TII, bool IsUnsigned, bool Int64, bool Float64, unsigned LoweredOpcode) argument 439 const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86FloatingPoint.cpp | 87 const TargetInstrInfo *TII = nullptr; // Machine instruction info. member in struct:__anon2498::FPS 241 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg); 251 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg); 342 TII = MF.getSubtarget().getInstrInfo(); 848 I->setDesc(TII->get(Opcode)); 852 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0); 883 return BuildMI(*MBB, I, DebugLoc(), TII->get(X86::ST_FPrr)) 941 BuildMI(*MBB, I, DebugLoc(), TII->get(X86::LD_F0)); 1109 MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode()))); 1155 MI.setDesc(TII [all...] |
H A D | X86InsertPrefetch.cpp | 188 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); local 212 const MCInstrDesc &Desc = TII->get(PFetchInstrID);
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H A D | X86AvoidStoreForwardingBlocks.cpp | 88 const X86InstrInfo *TII = nullptr; member in class:__anon2477::X86AvoidSFBPass 396 TII->getRegClass(TII->get(NLoadOpcode), 0, TRI, *(MBB->getParent()))); 398 BuildMI(*MBB, LoadInst, LoadInst->getDebugLoc(), TII->get(NLoadOpcode), 419 BuildMI(*MBB, StInst, StInst->getDebugLoc(), TII->get(NStoreOpcode)) 566 auto TRC = TII->getRegClass(TII->get(LoadInst->getOpcode()), 0, TRI, 680 TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
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H A D | X86CmovConversion.cpp | 116 const TargetInstrInfo *TII = nullptr; member in class:__anon2482::X86CmovConverterPass 171 TII = STI.getInstrInfo(); 693 BuildMI(MBB, DL, TII->get(X86::JCC_1)).addMBB(SinkMBB).addImm(CC); 761 bool Unfolded = TII->unfoldMemoryOperand(*MBB->getParent(), MI, TmpReg, 836 MIB = BuildMI(*SinkMBB, SinkInsertionPoint, DL, TII->get(X86::PHI), DestReg)
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFISelLowering.cpp | 566 const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo(); local 576 BuildMI(BB, DL, TII.get(BPF::MOV_32_64), PromotedReg0).addReg(Reg); 577 BuildMI(BB, DL, TII.get(BPF::SLL_ri), PromotedReg1) 579 BuildMI(BB, DL, TII.get(RShiftOp), PromotedReg2) 619 const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo(); local 723 BuildMI(BB, DL, TII.get(NewCC)).addReg(LHS).addReg(RHS).addMBB(Copy1MBB); 728 BuildMI(BB, DL, TII.get(NewCC)) 744 BuildMI(*BB, BB->begin(), DL, TII.get(BPF::PHI), MI.getOperand(0).getReg())
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsOptimizePICCall.cpp | 153 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); local 156 BuildMI(*MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), DstReg)
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonGenPredicate.cpp | 107 const HexagonInstrInfo *TII = nullptr; member in class:__anon2249::HexagonGenPredicate 275 BuildMI(B, std::next(DefIt), DL, TII->get(TargetOpcode::COPY), NewPR) 423 MachineInstrBuilder MIB = BuildMI(B, MI, DL, TII->get(NewOpc), NewPR.R); 437 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), NewOutR) 500 TII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
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