Searched refs:Subtarget (Results 126 - 150 of 170) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelDAGToDAG.cpp43 /// Subtarget - Keep a pointer to the BPFSubtarget around so that we can
45 const BPFSubtarget *Subtarget; member in class:__anon93::BPFDAGToDAGISel
49 : SelectionDAGISel(TM), Subtarget(nullptr) {}
57 Subtarget = &MF.getSubtarget<BPFSubtarget>();
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp58 : AMDGPUTargetLowering(TM, STI), Subtarget(&STI), Gen(STI.getGeneration()) {
69 computeRegisterProperties(Subtarget->getRegisterInfo());
178 if (Subtarget->hasCARRY())
181 if (Subtarget->hasBORROW())
185 if (!Subtarget->hasBFE())
191 if (!Subtarget->hasBFE())
196 if (!Subtarget->hasBFE())
225 if (!Subtarget->hasFMA()) {
233 if (!Subtarget->hasBFI()) {
239 if (!Subtarget
[all...]
H A DAMDGPUISelLowering.cpp67 : TargetLowering(TM), Subtarget(&STI) {
626 (ScalarVT == MVT::f16 && Subtarget->has16BitInsts()));
745 (Subtarget->has16BitInsts() && VT == MVT::f16);
751 (Subtarget->has16BitInsts() && VT == MVT::f16) ||
752 (Subtarget->hasVOP3PInsts() && VT == MVT::v2f16);
788 if (DestSize== 16 && Subtarget->has16BitInsts())
798 if (SrcSize == 16 && Subtarget->has16BitInsts())
2523 if (Subtarget->has16BitInsts() && DestVT == MVT::f16) {
2562 if (Subtarget->has16BitInsts() && DestVT == MVT::f16) {
2716 if (Subtarget
[all...]
H A DAMDGPURegisterBankInfo.cpp136 Subtarget(ST),
137 TRI(Subtarget.getRegisterInfo()),
138 TII(Subtarget.getInstrInfo()) {
747 const unsigned WaveAndOpc = Subtarget.isWave32() ?
749 const unsigned MovTermOpc = Subtarget.isWave32() ?
751 const unsigned XorTermOpc = Subtarget.isWave32() ?
753 const unsigned AndSaveExecOpc = Subtarget.isWave32() ?
755 const unsigned ExecReg = Subtarget.isWave32() ?
1261 if (!Subtarget.hasUnpackedD16VMem())
2642 if (Subtarget
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.h175 const AVRSubtarget &Subtarget; member in class:llvm::AVRTargetLowering
H A DAVRISelLowering.cpp36 : TargetLowering(TM), Subtarget(STI) {
42 computeRegisterProperties(Subtarget.getRegisterInfo());
169 if (!Subtarget.supportsMultiplication()) {
1281 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1443 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1582 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1898 Subtarget.getRegisterInfo(), Constraint, VT);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMMCInstLower.cpp102 if (Subtarget->genExecuteOnly())
H A DARMISelLowering.h476 return Subtarget;
639 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
641 const ARMSubtarget *Subtarget; member in class:llvm::ARMTargetLowering
685 const ARMSubtarget *Subtarget) const;
687 const ARMSubtarget *Subtarget) const;
H A DARMCallLowering.cpp420 auto Subtarget = TLI.getSubtarget(); local
422 if (Subtarget->isThumb1Only())
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.h54 const SparcSubtarget *Subtarget; member in class:llvm::SparcTargetLowering
H A DSparcTargetMachine.cpp102 Subtarget(TT, CPU, FS, *this, is64bit), is64Bit(is64bit) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h59 const RISCVSubtarget &Subtarget; member in class:llvm::RISCVTargetLowering
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp146 /// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can
148 const AArch64Subtarget *Subtarget; member in class:__anon2030::final
295 Subtarget =
353 return Subtarget->isTargetDarwin() ? CC_AArch64_DarwinPCS : CC_AArch64_AAPCS;
418 if (Subtarget->isTargetMachO() && TM.getCodeModel() == CodeModel::Large) {
461 if (!Subtarget->useSmallAddressing() && !Subtarget->isTargetMachO())
464 unsigned OpFlags = Subtarget->ClassifyGlobalReference(GV, TM);
480 if (Subtarget->isTargetILP32()) {
492 if (!Subtarget
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H A DAArch64LoadStoreOptimizer.cpp117 const AArch64Subtarget *Subtarget; member in struct:AArch64LoadStoreOpt
1054 if (!Subtarget->isLittleEndian())
2094 Subtarget = &static_cast<const AArch64Subtarget &>(Fn.getSubtarget());
2095 TII = static_cast<const AArch64InstrInfo *>(Subtarget->getInstrInfo());
2096 TRI = Subtarget->getRegisterInfo();
2107 bool enableNarrowZeroStOpt = !Subtarget->requiresStrictAlign();
H A DAArch64InstrInfo.h40 const AArch64Subtarget &Subtarget; member in class:llvm::final
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.h547 const SystemZSubtarget &Subtarget; member in class:llvm::SystemZTargetLowering
698 bool isVectorConstantLegal(const SystemZSubtarget &Subtarget);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp119 Subtarget(ST) {}
791 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
987 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1621 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1651 if (!Subtarget.usePredicatedCalls())
1656 if (!Subtarget.hasV62Ops()) {
1757 return new HexagonHazardRecognizer(II, this, Subtarget);
2092 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
3046 Subtarget.hasV60Ops();
3051 if (MI.mayStore() && !Subtarget
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H A DHexagonInstrInfo.h39 const HexagonSubtarget &Subtarget; member in class:llvm::HexagonInstrInfo
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRuntimeLibcallSignatures.cpp512 void llvm::getLibcallSignature(const WebAssemblySubtarget &Subtarget, argument
520 Subtarget.hasAddr64() ? wasm::ValType::I64 : wasm::ValType::I32;
881 void llvm::getLibcallSignature(const WebAssemblySubtarget &Subtarget, argument
893 return getLibcallSignature(Subtarget, Val->second, Rets, Params);
H A DWebAssemblyAsmPrinter.cpp58 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/
H A DMIParser.cpp90 if (&Subtarget == &NewSubtarget)
112 const auto *TRI = Subtarget.getRegisterInfo();
137 const auto *TII = Subtarget.getInstrInfo();
156 const auto *TRI = Subtarget.getRegisterInfo();
177 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
194 const auto *TII = Subtarget.getInstrInfo();
214 const auto *TII = Subtarget.getInstrInfo();
236 const auto *TII = Subtarget.getInstrInfo();
258 const auto *TII = Subtarget.getInstrInfo();
279 const TargetRegisterInfo *TRI = Subtarget
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp74 const XCoreSubtarget &Subtarget)
75 : TargetLowering(TM), TM(TM), Subtarget(Subtarget) {
81 computeRegisterProperties(Subtarget.getRegisterInfo());
783 const TargetRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
829 const TargetRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
1526 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
73 XCoreTargetLowering(const TargetMachine &TM, const XCoreSubtarget &Subtarget) argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp45 Subtarget = &static_cast<const NVPTXSubtarget &>(MF.getSubtarget());
50 return Subtarget->getTargetLowering()->getDivF32Level();
54 return Subtarget->getTargetLowering()->usePrecSqrtF32();
58 return Subtarget->getTargetLowering()->useF32FTZ(*MF);
62 const NVPTXTargetLowering *TL = Subtarget->getTargetLowering();
67 const NVPTXTargetLowering *TL = Subtarget->getTargetLowering();
676 static bool canLowerToLDG(MemSDNode *N, const NVPTXSubtarget &Subtarget, argument
695 if (!Subtarget.hasLDG() || CodeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL)
864 if (canLowerToLDG(LD, *Subtarget, CodeAddrSpace, MF)) {
1008 if (canLowerToLDG(MemSD, *Subtarget, CodeAddrSpac
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.cpp217 // Wrapper for Tablegen'd function. enum Subtarget is not defined in any
221 return getMCOpcodeGen(Opcode, static_cast<Subtarget>(Gen));
1270 const GCNSubtarget *Subtarget, uint32_t Align) {
1300 Subtarget->getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS)
H A DAMDGPUBaseInfo.h661 const GCNSubtarget *Subtarget, uint32_t Align = 4);

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